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ADV7480WBBCZ

Dual Mode HDMI/MHL Receiver

Analog Devices 

ADV7480

COMPONENT PROCESSOR

The ADV7480 has one any-to-any 3 × 3 CSC matrix. The CSC

block is located in the processing path before the CP section.

CSC enables YCbCr-to-RGB and RGB-to-YCbCr conversions.

Many other standards of color space can be implemented using

the color space converter.

CP features include

• Support for all video modes supported by the HDMI/MHL

receiver. These include 525i, 625i, 525p, 625p, 1080i, 1080p,

and display resolutions from VGA (640 × 480 at 60 Hz) to

UXGA (1600 × 1200 at 60 Hz).

• Manual adjustments including gain (contrast), offset

(brightness), hue, and saturation.

• Free run output mode that provides stable timing when no

video input is present.

• Timing adjustments controls for HS/VS/DE timing.

8-BIT DIGITAL INPUT/OUTPUT PORT

The ADV7480 features an 8-bit digital bidirectional port. The

following formats are supported both as input and output ports:

• 8-bit interleaved 4:2:2 SDR input/output with embedded

timing codes

• 8-bit interleaved 4:2:2 DDR input/output with embedded

timing codes

The maximum input and output video resolution supported is

720p/1080i in both SDR and DDR modes.

Video received on the 8-bit digital input port can be routed to

the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit

digital output port can be routed from the CP core.

AUDIO PROCESSING

The ADV7480 features an audio processor that handles the

audio extracted from the MHL or HDMI stream by the

HDMI/MHL receiver. It contains an audio mute controller that

can detect a variety of conditions that may result in audible

extraneous noise in the audio output. On detection of these

conditions, a 2-channel linear PCM audio signal can be ramped

down to a mute state to prevent audio clicks or pops.

Data Sheet

The audio is output on a single flexible serial digital audio

output port supporting I2S-compatible, left justified and right

justified audio output modes in master mode only. TDM is also

supported, allowing up to eight audio channels with a sample

rate up to 48 kHz to be transmitted over the single serial digital

audio interface.

MIPI CSI-2 TRANSMITTER

The ADV7480 features one MIPI CSI-2 transmitter

(Transmitter A).

The four-lane transmitter consists of four differential data lanes

(DA0N, DA0P, DA1N, DA1P, DA2N, DA2P, DA3N and DA3P),

and a differential clock lane (CLKAN and CLKAP). It supports

four data lanes, two data lanes and one data lane muxing

options, and can be used to transmit video received on either

the HDMI/MHL receiver (processed through the CP) or the

8-bit digital input port.

The main features of the 4-lane MIPI transmitter

(Transmitter A) include

• Support for 8-bit and 10-bit YCbCr 4:2:2 video modes.

• Support for 24-bit RGB 4:4:4 (RGB888), 18-bit RGB 4:4:4

(RGB666), and 16-bit RGB 4:4:4 (RGB565) video modes.

• Support for video formats ranging from 480i to 1080p, and

display resolutions from VGA to UXGA (certain

restrictions apply to the muxing option, video mode, and

video format that can be selected).

• Data lanes and clock lane remapping to ease PCB layout.

INTERRUPTS

The ADV7480 features three interrupt request pins. INTRQ1

and INTRQ2 can be programmed to trigger interrupts based on

various selectable events related to the HDMI/MHL receiver

(video and audio related) and the CP. INTRQ3 is dedicated to

events related to the MHL CBUS.

Rev. 0 | Page 18 of 19

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