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CS5505
(Rev.:2009)

Very Low Power, 16-Bit & 20-Bit A/D Converters

Cirrus Logic 

CS5505/6/7/8

CS5505/6/7/8

If the CS5505/6/7/8 is operated at a clock rate

other than 32.768 kHz, the filter characteristics,

including the comb filter zeros, will scale with

the operating clock frequency. Therefore, opti-

mum rejection of line frequency interference will

occur with the CS5505/6/7/8 running at

32.768 kHz. The CS5505/6/7/8 can be used with

external clock rates from 30 kHz to 163 kHz.

Anti-Alias Considerations for Spectral

Measurement Applications

Input frequencies greater than one half the out-

put word rate (CONV = 1) may be aliased by

the converter. To prevent this, input signals

should be limited in frequency to no greater than

one half the output word rate of the converter

(when CONV =1). Frequencies close to the

modulator sample rate (XIN/2) and multiples

thereof may also be aliased. If the signal source

includes spectral components above one half the

output word rate (when CONV = 1) these com-

ponents should be removed by means of low-

pass filtering prior to the A/D input to prevent

aliasing. Spectral components greater than one

half the output word rate on the VREF inputs

(VREF+ and VREF-) may also be aliased. Fil-

tering of the reference voltage to remove these

spectral components from the reference voltage

is desirable.

Crystal Oscillator

The CS5505/6/7/8 is designed to be operated us-

ing a 32.768 kHz "tuning fork" type crystal. One

end of the crystal should be connected to the

XIN input. The other end should be attached to

XOUT. Short lead lengths should be used to

minimize stray capacitance. Figure 12 illustrates

the gate oscillator, and a simplified version of

the control logic used on the chip.

Over the industrial temperature range (-40 to

+85 °C) the on-chip gate oscillator will oscillate

CS5505/6

Channel A0 A1

A0

DQ

1

00

CLK

Input

2

01

Mux

A1

DQ

Decoder

3

10

4

11

CLK

CONV

CAL

R

10 MΩ

22.5 pF 15 pF

gm ~~19 umho

SQ

R

SQ

R

Q

T

D

Q

Start

Conversion

CLK

D Q Start

Calibration

CLK

Modulator

Sample

Clock

XOUT

XIN

XTL=32.768 kHz

Figure 12. Gate Oscillator and Control Logic

2200

DS59F74

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