CS5505(2009) Ver la hoja de datos (PDF) - Cirrus Logic
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CS5505 Datasheet PDF : 40 Pages
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CS5505/6/7/8
CS5505/6/7/8
3.3V SWITCHING CHARACTERISTICS (TA = T MIN to TMAX VA+ = 5V ± 10%;
VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+ ; CL = 50 pF.) (Note 2)
Parameter
Symbol
Master Clock Frequency:
Internal Oscillator:
External Clock:
-A,B XIN
-S or
fclk
Master Clock Duty Cycle
Rise Times:
Any Digital Input (Note 10) trise
Any Digital Output
Fall Times:
Any Digital Input (Note 10) tfall
Any Digital Output
Start-Up
Power-On Reset Period
Oscillator Start-up Time
Wake-up Period
Calibration
(Note 11) tres
XTAL=32.768 kHz (Note 12) tosu
(Note 13) twup
CONV Pulse Width (CAL = 1)
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration
Conversion
(Note 14) tccw
tscl
tcal
Set Up Time
A0, A1 to CONV High
tsac
Hold Time
A0, A1 after CONV High
thca
CONV Pulse Width
tcpw
CONV High to Start of Conversion
tscn
Set Up Time
BP/UP stable prior to DRDY fal ling tbus
Hold Time
BP/UP stable after DRDY fal ls tbuh
Start of Conversion to End of Conversion
(Note 15) tcon
Min
30.0
30.0
30
40
-
-
-
-
-
-
-
100
-
-
50
100
100
-
82/fclk
0
-
Typ
32.768
32.768
-
-
-
50
-
20
Max Units
53.0 kHz
34.0 kHz
163 kHz
60
%
1.0
µs
-
ns
1.0
µs
-
ns
10
-
ms
500
-
ms
1800/fclk
-
s
-
-
ns
-
2/fclk+200 ns
3246/fclk
-
s
-
-
ns
-
-
ns
-
-
ns
-
2/fclk+200 ns
-
-
s
-
-
ns
1624/fclk
-
s
DS59F74
7
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