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EPCS16

Serial Configuration (EPCS) Devices

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Active Serial FPGA Configuration

Figure 1 shows the EPCS device block diagram.

Figure 1. EPCS Device Block Diagram

EPCS Device

nCS

DCLK

Control

Logic

I/O Shift

Register

DATA

ASDI

Page 3

Address Counter

Data Buffer

Status Register

Decode Logic

Memory

Array

Accessing Memory in EPCS Devices

You can access the unused memory locations of the EPCS device to store or retrieve

data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for

creating bus-based (especially microprocessor-based) systems in Altera devices.

SOPC Builder assembles library components such as processors and memories into

custom microprocessor systems.

SOPC Builder includes the EPCS device controller core, which is an interface core

designed specifically to work with the EPCS device. With this core, you can create a

system with a Nios embedded processor that allows software access to any memory

location within the EPCS device.

Active Serial FPGA Configuration

The following Altera FPGAs support the AS configuration scheme with EPCS devices:

■ Arria series

■ Cyclone series

■ All device families in the Stratix series except the Stratix device family

There are four signals on the EPCS device that interface directly with the FPGA’s

control signals. The EPCS device signals are DATA, DCLK, ASDI, and nCS interface with

the DATA0, DCLK, ASDO, and nCSO control signals on the FPGA, respectively.

1 For more information about the EPCS device pin description, refer to Table 23 on

page 36.

April 2014 Altera Corporation

Serial Configuration (EPCS) Devices Datasheet

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