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V363EPC

Local Bus to PCI Bridge for Embedded Processors

QuickLogic Corporation 

Pin Descriptions and Pinouts

Test Mode Pins

3.1 Test Mode Pins

Several device pins are used during the manufacturing test to put the V363EPC device into various test modes.

Note: These pins must be maintained at proper levels during reset to insure proper

operation.

This is typically handled through pull-up or pull-down resistors (typically 1–10 kΩ) on the signal pins if they are not

guaranteed to be at the proper level during reset. Table 5 shows the reset states for test mode pins.

Table 5: RESET State for Test Mode Pins

Mode

i960 Cx/Hx

AMD 2930/40

i960 Jx

i960 Sx

Pin 134

Pull up

Pull down

Pull down

Pull down

Pin 135

Pull up

Pull up

Pull up

Pull down

Pin 153

Pull up

Pull up

Pull down

Pull down

3.2 Processor-mode Specific Pin Assignments

The following tables and diagrams describe the pin assignments for the V363EPC A0 in its various processor modes.

• AM29030/040 mode: Table 6 and Figure 2

• i960 Cx/Hx mode: Table 7 and Figure 3

• i960 Jx mode: Table 8 and Figure 4

• i960 Sx mode: Table 9 and Figure 5

© 2000 V3 Semiconductor Corp.

V363EPC A0 Data Sheet Rev 1.01 DS-EC301-0101

7

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