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V350EPC-33

LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V350EPC

Signal

LAD[31:0]

LAD[15:0]b

LA[31:16]b

LA[5:2]

ALE

BE[3:0]

BE[1:0]b

W/R

ADS

ASb

RDYRCV

READYb

HOLD

HOLDA

LPAR[3:0]

LPAR[1:0]b

BLAST

BTERMc

LINT

LRST

LCLK

Table 3: Signal Descriptions (cont’d)

Type

Local Bus Interface

R Description

I/O4

Z Local multiplexed address and data bus.

I/O4

Z Local address bus.

O4

Lower local address bus (non-multiplexed version).

I/O4

Z

Address Latch Enable: used to latch the address during the

address phase.

I/O4

Z Local bus byte enables.

I/O4

Z Write/Read.

I/O4

Z Asserted low to indicate the beginning of a bus cycle.

I/O4

Z Local Bus data ready

O4

L

Local bus hold request: asserted by the chip to initiate a local bus

master cycle.

I

Local bus hold acknowledge.

I/O4

Z Local bus parity.

I/O4

Z Burst last.

I/O4

Z Bus Time-out. Burst terminate.

O4

H Local interrupt request.

I/O4 L/Z Local bus RESET signal.

I

Local bus clock.

Signal

SCL/LPERR

SDA

Type

O4

I/O4

Serial EEPROM Interface

R Description

X EEPROM clock. Local parity error.

X EEPROM data.

4

V350EPC Data Sheet Rev 1.1

Copyright © 1998, V3 Semiconductor Inc.

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