V961PBC-40REVB2 Ver la hoja de datos (PDF) - QuickLogic Corporation

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V961PBC-40REVB2

LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V961PBC

Table 3: Signal Descriptions (cont’d)

Power and Ground Signals

Signal

Type R

Description

VCC

-

POWER leads intended for external connection to a VCC board

plane.

GND

-

GROUND leads intended for external connection to a GND board

plane.

a. R indicates state during reset.

2.1 Test Mode Pins

Several device pins are used during manufacturing test to put the V961PBC device into various test

modes. These pins must be maintained at proper levels during reset to insure proper operation.

This is typically handled through pull-up or pull-down resistors (typically 1K to 10K) on the signal pins if

they are not guaranteed to be at the proper level during reset. Table 4 below shows the reset states for

test mode pins:

Table 4: RESET State for Test Mode Pins

PIN#

Connection

134

Pull-Down

135

Pull-Up

153

Pull-Down

PIN #

1

2

3

4

5

6

7

8

Signal

VCC

INTD

PRST

PCLK

GNT

REQ

AD31

AD30

Table 5: Pin Assignments

PIN #

41

42

43

44

45

46

47

48

Signal

VCC

AD14

AD13

AD12

AD11

AD10

AD9

AD8

PIN #

81

82

83

84

85

86

87

88

Signal

VCC

NC

LAD8

NC

LAD9

NC

LAD10

NC

PIN #

121

122

123

124

125

126

127

128

Signal

VCC

NC

LAD25

LA5

LAD26

LA4

LAD27

LA3

Copyright © 1998, V3 Semiconductor Inc.

V961PBC Data Sheet Rev 2.4

5

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