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GS72116AJ

128K x 16 2Mb Asynchronous SRAM

Giga Semiconductor 

AC Characteristics

GS72116ATP/J/T/U

Read Cycle

Parameter

Read cycle time

Address access time

Chip enable access time (CE)

Byte enable access time (UB, LB)

Output enable to output valid (OE)

Output hold from address change

Chip enable to output in low Z (CE)

Output enable to output in low Z (OE)

Byte enable to output in low Z (UB, LB)

Chip disable to output in High Z (CE)

Output disable to output in High Z (OE)

Byte disable to output in High Z (UB, LB)

Symbol

tRC

tAA

tAC

tAB

tOE

tOH

tLZ*

tOLZ*

tBLZ*

tHZ*

tOHZ*

tBHZ*

-7

Min Max

7

—

—

7

—

7

—

3

—

3

3

—

3

—

0

—

0

—

—

3.5

—

3

—

3

* These parameters are sampled and are not 100% tested.

-8

Min Max

8

—

—

8

—

8

—

3.5

—

3.5

3

—

3

—

0

—

0

—

—

4

—

3.5

—

3.5

-10

Min Max

10

—

—

10

—

10

—

4

—

4

3

—

3

—

0

—

0

—

—

5

—

4

—

4

-12

Unit

Min Max

12

—

ns

—

12

ns

—

12

ns

—

5

ns

—

5

ns

3

—

ns

3

—

ns

0

—

ns

0

—

ns

—

6

ns

—

5

ns

—

5

ns

Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL

Address

Data Out

tOH

Previous Data

tRC

tAA

Data valid

Rev: 1.04a 10/2002

7/18

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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