USB3319-CP-TR(2007) Ver la hoja de datos (PDF) - SMSC -> Microchip
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USB3319-CP-TR
(Rev.:2007)
(Rev.:2007)
SMSC -> Microchip
USB3319-CP-TR Datasheet PDF : 12 Pages
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Hi-Speed USB Transceiver with 1.8V ULPI Interface - 13MHz Reference Clock
PIN/
BALL
4
D2
5
D1
6
E1
7
E2
8
E3
9
D3
10
E4
11
D4
12
E5
13
D5
14
C4
15
C5
16
B4
17
B5
18
A5
19
A4
SMSC USB3319
Table 1 USB3319 Pin Description (continued)
NAME
VDD3.3
DM
DP
SPKR_R/M
SPKR_L
DATA[7]
DATA[6]
DATA[5]
DATA[4]
CLKOUT
DATA[3]
DATA[2]
DATA[1]
DATA[0]
NXT
DIR
DIRECTION/ ACTIVE
TYPE
LEVEL
DESCRIPTION
Power
N/A 3.3V Regulator Output. A 2.2uF (<1 ohm
ESR) bypass capacitor to ground is
required for regulator stability. The
bypass capacitor should be placed as
close as possible to the USB3319.
I/O,
Analog
N/A D- pin of the USB cable.
I/O,
Analog
N/A D+ pin of the USB cable.
I/O,
Analog
N/A USB switch in/out for DP signals
I/O,
Analog
N/A USB switch in/out for DM signals
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
Output,
CMOS
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
I/O,
CMOS
Output,
CMOS
Output,
CMOS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
High
N/A
ULPI bi-directional data bus. DATA[7] is
the MSB.
ULPI bi-directional data bus.
ULPI bi-directional data bus.
ULPI bi-directional data bus.
60MHz reference clock output. All ULPI
signals are driven synchronous to the
rising edge of this clock.
ULPI bi-directional data bus.
ULPI bi-directional data bus.
ULPI bi-directional data bus.
ULPI bi-directional data bus. DATA[0] is
the LSB.
The PHY asserts NXT to throttle the data.
When the Link is sending data to the
PHY, NXT indicates when the current
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
Controls the direction of the data bus.
When the PHY has data to transfer to the
Link, it drives DIR high to take ownership
of the bus. When the PHY has no data to
transfer it drives DIR low and monitors
the bus for commands from the Link.
7
PRODUCT PREVIEW
Revision 1.3 (11-02-07)
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