CYUSB3031-BZXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CYUSB3031-BZXC Datasheet PDF : 54 Pages
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CYUSB303X
JTAG Interface
FX3S’s JTAG interface has a standard five-pin interface to
connect to a JTAG debugger in order to debug firmware through
the CPU-core’s on-chip-debug circuitry.
Industry-standard debugging tools for the ARM926EJ-S core
can be used for the FX3S application development.
Other Interfaces
FX3S supports the following serial peripherals:
■ UART
■ I2C
■ I2S
■ SPI
The SPI, UART, and I2S interfaces are multiplexed on the serial
peripheral port.
UART Interface
The UART interface of FX3S supports full-duplex
communication. It includes the signals noted in Table 1.
Table 1. UART Interface Signals
Signal
TX
RX
CTS
RTS
Description
Output signal
Input signal
Flow control
Flow control
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then FX3S's UART only transmits data when the CTS
input is asserted. In addition to this, FX3S's UART asserts the
RTS output signal, when it is ready to receive data.
I2C Interface
FX3S’s I2C interface is compatible with the I2C Bus Specification
Revision 3. This I2C interface is capable of operating only as I2C
master; therefore, it may be used to communicate with other I2C
slave devices. For example, FX3S may boot from an EEPROM
connected to the I2C interface, as a selectable boot option.
FX3S’s I2C Master Controller also supports multi-master mode
functionality.
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This
gives the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I2C controller supports the clock-stretching
feature to enable slower devices to exercise flow control.
The I2C interface’s SCL and SDA signals require external pull-up
resistors. The pull-up resistors must be connected to VIO5.
I2S Interface
FX3S has an I2S port to support external audio codec devices.
FX3S functions as I2S Master as transmitter only. The I2S
interface consists of four signals: clock line (I2S_CLK), serial
data line (I2S_SD), word select line (I2S_WS), and master
system clock (I2S_MCLK). FX3S can generate the system clock
as an output on I2S_MCLK or accept an external system clock
input on I2S_MCLK.
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
SPI Interface
FX3S supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 47 for details on the
modes) with the Start-Stop clock. This controller is a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
Document Number: 001-84160 Rev. *G
Page 11 of 54
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