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SCC68681

Dual asynchronous receiver/transmitter (DUART)

NXP Semiconductors. 

Philips Semiconductors

Dual asynchronous receiver/transmitter (DUART)

Product data

SCC68681

PIN CONFIGURATIONS

A1 1

IP3 2

40 VCC

39 IP4

A2 3

38 IP5

IP1 4

37 IACKN

A3 5

36 IP2

A4 6

35 CSN

IP0 7

34 RESETN

R/WN 8

33 X2

DTACKN 9

32 X1/CLK

RxDB 10

31 RxDA

DIP

TxDB 11

30 TxDA

OP1 12

29 OP0

OP3 13

28 OP2

OP5 14

27 OP4

OP7 15

26 OP6

D1 16

25 D0

D3 17

24 D2

D5 18

23 D4

D7 19

22 D6

GND 20

21 INTRN

6

7

1

40

39

PLCC

17

18

1 NC

2 A1

3 IP3

4 A2

5 IP1

6 A3

7 A4

8 IP0

9 R/WN

10 DTACKN

11 RxDB

12 NC

13 TxDB

14 OP1

15 OP3

29

28

PIN/FUNCTION

16 OP5

17 OP7

18 D1

19 D3

20 D5

21 D7

22 GND

23 NC

24 INTRN

25 D6

26 D4

27 D2

28 D0

29 OP6

30 OP4

31 OP2

32 OP0

33 TxDA

34 NC

35 RxDA

36 X1/CLK

37 X2

38 RESETN

39 CSN

40 IP2

41 IACKN

42 IP5

43 IP4

44 VCC

Figure 1. Pin Configurations

SD00107

PIN DESCRIPTION

SYMBOL

PIN

TYPE

NAME AND FUNCTION

PLCC44 DIP40

D0–D7

28, 18,

27, 19,

26, 20,

25, 21

25, 16,

24, 17,

23, 18,

22, 19

I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between

the DUART and the CPU. D0 is the least significant bit.

CSN

39

35

I Chip Select: Active-LOW input signal. When LOW, data transfers between the CPU and the

DUART are enabled on D0–D7 as controlled by the R/WN, RDN and A1–A4 inputs. When HIGH,

places the D0–D7 lines in the 3-State condition.

R/WN

9

8

I Read/Write: A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a

cycle is initiated by assertion of the CSN input.

A1–A4 2, 4, 6, 7 1, 3, 5, 6 I Address Inputs: Select the DUART internal registers and ports for read/write operations.

RESETN

38

34

I Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the

IVR to hex 0F, puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channel A and

B in the inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test

modes, sets MR pointer to MR1.

DTACKN

10

9

O Data Transfer Acknowledge: Three-state active LOW output asserted in write, read, or interrupt

cycles to indicate proper transfer of data between the CPU and the DUART.

INTRN

24

21

O Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or more of

the eight maskable interrupting conditions are true.

IACKN

41

37

I Interrupt Acknowledge: Active-LOW input indicating an interrupt acknowledge cycle. In

response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it

has an interrupt pending.

2004 Apr 06

3

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