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A4986

DMOS Dual Full-Bridge PWM Motor Driver

Allegro MicroSystems 

A4986

DMOS Dual Full-Bridge PWM Motor Driver

with Overcurrent Protection

source-side FET gates. A 0.1 μF ceramic capacitor, should be

connected between CP1 and CP2. In addition, a 0.1 μF ceramic

capacitor is required between VCP and VBB, to act as a reservoir

for operating the high-side FET gates.

Capacitor values should be Class 2 dielectric ±15% maximum,

or tolerance R, according to EIA (Electronic Industries Alliance)

specifications.

VREG (VREG). This internally-generated voltage is used to oper-

ate the sink-side FET outputs. The VREG pin must be decoupled

with a 0.22 μF ceramic capacitor to ground. VREG is internally

monitored. In the case of a fault condition, the FET outputs of the

A4986 are disabled.

Capacitor values should be Class 2 dielectric ±15% maximum,

or tolerance R, according to EIA (Electronic Industries Alliance)

specifications.

Shutdown. In the event of a fault, overtemperature (excess TJ)

or an undervoltage (on VCP), the FET outputs of the A4986 are

disabled until the fault condition is removed. At power-on, the

UVLO (undervoltage lockout) circuit disables the FET outputs

and resets the translator to the Home state.

Sleep Mode ( ¯S¯¯L¯¯E¯¯E¯¯P¯ ). To minimize power consumption

when the motor is not in use, this input disables much of the

internal circuitry including the output FETs, current regulator, and

charge pump. A logic low on the SLEEP pin puts the A4986 into

Sleep mode. When emerging from Sleep mode, in order to allow

the charge pump to stabilize, provide a delay of 1 ms before issu-

ing a logic command.

Mixed Decay Operation. The bridge operates in Mixed

Decay mode, as shown in figures 5 through 7. As the trip point

is reached, the A4986 initially goes into a fast decay mode for

31.25% of the off-time, tOFF. After that, it switches to Slow Decay

mode for the remainder of tOFF. A timing diagram for this feature

appears in figure 4.

Synchronous Rectification. When a PWM-off cycle is

triggered by an internal fixed-off time cycle, load current recir-

culates in Mixed Decay mode. This synchronous rectification

feature turns on the appropriate FETs during current decay, and

effectively shorts out the body diodes with the low FET RDS(ON).

This reduces power dissipation significantly, and can eliminate

the need for external Schottky diodes in many applications. Syn-

chronous rectification turns off when the load current approaches

zero (0 A), preventing reversal of the load current.

5 A / div.

Fault

latched

t→

Figure 1. Short-to-ground event

5 A / div.

Fixed off-time

t→

Figure 2. Shorted load (OUTxA → OUTxB) in

Slow decay mode

5 A / div.

Fixed off-time

Fast decay portion

(direction change)

t→

Figure 3. Shorted load (OUTxA → OUTxB) in Mixed decay mode

Allegro MicroSystems, Inc.

7

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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