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ALC888S

7.1+2 CHANNEL HIGH DEFINITION AUDIO CODEC WITH TWO INDEPENDENT S/PDIF-OUT

Realtek Semiconductor 

ALC888S & ALC888SDD

Datasheet

7.3.3. Codec Initialization Sequence

n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the

controller

o The codec will stop driving the SDI during this turnaround period

pqrs The controller drives SDI to assign a CAD to the codec

t The controller releases the SDI after the CAD has been assigned

u Normal operation state

Exit from Reset Connection Frame

Turnaround Frame

(Non-48kHz Frame)

Address Frame

(Non-48kHz Frame)

Normal Operation

BCLK

SYNC

SDIx

RST#

Frame SYNC

Frame SYNC

Frame SYNC

1

2

3

45

SD0 SD1

6

SD14

7

8

Response

Codec

Drives SDIx

Codec

Turnaround

(477 BCLK

Max.)

Figure 15.

Controller Drives SDIx

Controller

Turnaround

(477 BCLK

Max.)

Codec Initialization Sequence

Codec Drives SDIx

7.4. Verb and Response Format

7.4.1. Command Verb Format

There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with

12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command

stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and

controls parameters in the codec.

Bit [39:32]

Reserved

Table 10. 40-Bit Commands in 4-Bit Verb Format

Bit [31:28]

Bit [27:20]

Bit [19:16]

Codec Address

Node ID

Verb ID

Bit [15:0]

Payload

Bit [39:32]

Reserved

Table 11. 40-Bit Commands in 12-Bit Verb Format

Bit [31:28]

Bit [27:20]

Bit [19:8]

Codec Address

Node ID

Verb ID

Bit [7:0]

Payload

7.1+2 Channel High Definition Audio Codec

22

w/Two Independent S/PDIF-OUT

Track ID: JATR-1076-21 Rev. 1.2

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