MT8880C Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
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MT8880C Datasheet PDF : 22 Pages
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MT8880C ISO2-CMOS
IN+ 1
IN- 2
GS 3
VRef 4
VSS 5
OSC1 6
OSC2 7
TONE 8
R/W 9
CS 10
20 VDD
19 St/GT
18 ESt
17 D3
16 D2
15 D1
14 D0
13 IRQ/CP
12 Φ2
11 RS0
20 PIN PLASTIC DIP/SOIC
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W
CS
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
24 PIN SSOP
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
Φ2
RS0
NC
VRef
VSS
OSC1
OSC2
NC
NC
Figure 2 - Pin Connections
5
•
6
7
8
9
10
11
28 PIN PLCC
25 NC
24 NC
23 NC
22 D3
21 D2
20 D1
19 D0
Pin Description
Pin #
20 24 28 Name
Description
1 1 1 IN+ Non-inverting op-amp input.
2 2 2 IN- Inverting op-amp input.
3 3 4 GS Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44
55
66
6 VRef Reference Voltage output, nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 13).
7 VSS Ground input (0V).
8 OSC1 DTMF clock/oscillator input. Connect a 4.7MΩ resistor to VSS if crystal oscillator is used.
77
9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the
internal oscillator circuit. Leave open circuit when OSC1 is clock input.
8 10 12 TONE Tone output (DTMF or single tone).
9 11 13 R/W Read/Write input. Controls the direction of data transfer to and from the MPU and the
transceiver registers. TTL compatible.
10 12 14 CS Chip Select, TTL input (CS=0 to select the chip).
11 13 15 RS0 Register Select input. See register decode table. TTL compatible.
12 14 17 Φ2 System Clock input. TTL compatible. N.B. Φ2 clock input need not be active when the
device is not being accessed.
13 15 18 IRQ/ Interrupt Request to MPU (open drain output). Also, when call progress (CP) mode has
CP been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be
within the bandwidth limits of the call progress filter. See Figure 8.
14- 18- 19-22 D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS = 1 or Φ2 is low.
17 21
18 22 26 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19 23
27 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St
causes the device to register the detected tone pair and update the output latch. A voltage
less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 28 VDD Positive power supply input (+5V typical).
8, 9, 3,5,10, NC No Connection.
16,17 11, 16,
23-25
2
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