BS62LV1027H Ver la hoja de datos (PDF) - Brilliance Semiconductor
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BS62LV1027H Datasheet PDF : 11 Pages
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n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
VCC
CE2
VCC
tCDR
VIL
Data Retention Mode
VDR≧1.5V
CE2≦0.2V
BS62LV1027
VCC
tR
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
Output Load
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
Others
Vcc / 0V
1V/ns
0.5Vcc
CL = 5pF+1TTL
CL = 30pF+1TTL
Output
1 TTL
CL(1)
VCC
GND
1. Including jig and scope capacitance.
ALL INPUT PULSES
90%
10%
→←
Rise Time :
1V/ns
90%
10%
→←
Fall Time :
1V/ns
WAVEFORM INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
MAY CHANGE
FROM “L” TO “H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE CHANGE
FROM “L” TO “H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
tAVAX
tAVQX
tE1LQV
tE2HQV
tGLQV
tE1LQX
tE2HQX
tGLQX
tE1HQZ
tE2LQZ
tGHQZ
tAVQX
PARAMETER
NAME
DESCRIPTION
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC = 3.0~5.5V)
(VCC = 2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
tRC
Read Cycle Time
55
--
--
70
--
--
tAA
Address Access Time
--
--
55
--
--
70
tACS1
Chip Select Access Time
(CE1) --
--
55
--
--
70
tACS2
Chip Select Access Time
(CE2) --
--
55
--
--
70
tOE
Output Enable to Output Valid
--
--
30
--
--
35
tCLZ1
Chip Select to Output in Low Z
(CE1) 10
--
--
10
--
--
tCLZ2
Chip Select to Output in Low Z
(CE2) 10
--
--
10
--
--
tOLZ
Output Enable to Output in Low Z
5
--
--
5
--
--
tCHZ1
Chip Deselect to Output in High Z (CE1) --
--
30
--
--
35
tCHZ2
Chip Deselect to Output in High Z (CE2) --
--
30
--
--
35
tOHZ
Output Disable to Output in High Z
--
--
25
--
--
30
tOH
Data Hold from Address Change
10
--
--
10
--
--
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS62LV1027
4
Revision 2.3
May.
2006
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