MT8960/61/62/63/64/65/66/67
C2i
INPUT
F1i
125 µs
INTERNAL
ENABLE
DSTo
OUTPUT
76543210
HIGH IMPEDANCE
DSTi
INPUT
5V
CA
(Mode 3)
0V
76543210
CSTi
INPUT
LOAD
A-REGISTER
LOAD
B-REGISTER
76543210
76543210
Figure 9a - Timing Diagram - 125 µs Frame Period
Data Sheet
7
76
76
21
Zarlink Semiconductor Inc.