F71882 Ver la hoja de datos (PDF) - Feature Integration Technology Inc.
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Lista de partido
F71882 Datasheet PDF : 130 Pages
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O8-u47-5v
O8
O12
O30
AOUT
OD12
OD12-5v
OD24
INt5v
INts
INts5v
AIN
P
F71882
capability.
- Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
- Output pin with 8 mA source-sink capability.
- Output pin with 12 mA source-sink capability.
- Output pin with 30 mA source-sink capability.
- Output pin(Analog).
- Open-drain output pin with 12 mA sink capability.
- Open-drain output pin with 12 mA sink capability, 5V tolerance.
- Open-drain output pin with 24 mA sink capability.
- TTL level input pin,5V tolerance.
- TTL level input pin and schmitt trigger.
- TTL level input pin and schmitt trigger, 5V tolerance.
- Input pin(Analog).
- Power.
6.1 Power Pin
Pin No.
4,37,99
68
86
88
20, 48, 73, 117
Pin Name
VCC
VSB
VBAT
AGND(D-)
GND
Type
P
P
P
P
P
Description
Power supply voltage input with 3.3V
Stand-by power supply voltage input 3.3V
Battery voltage input
Analog GND
Digital GND
6.2 LPC Interface
Pin No. Pin Name
29
LRESET#
Type
INts5v
30
LDRQ#
31
SERIRQ
32
LFRAM#
O12
I/O12t
INts
36-33 LAD[3:0]
I/O12t
38
PCICLK
INts
39
CLKIN
INts
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Description
Reset signal. It can connect to PCIRST# signal on the
host.
Encoded DMA Request signal.
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a
broken cycle.
These signal lines communicate address, control, and
data information over the LPC bus between a host and
a peripheral.
33MHz PCI clock input.
System clock input. According to the input frequency
24/48MHz.
6.3 FDC
Pin No. Pin Name
7
DENSEL#
8
MOA#
Type
OD24
OD24
PWR
VCC
VCC
Description
Drive Density Select.
Set to 1 - High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
Motor A On. When set to 0, this pin enables disk drive
0. This is an open drain output.
-6-
May, 2008
V0.28P
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