LTC6820 Ver la hoja de datos (PDF) - Linear Technology
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LTC6820 Datasheet PDF : 28 Pages
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LTC6820
Operation
On the other side of the isolation barrier (i.e., the other end
of the cable) another LTC6820 is configured to interface
with a SPI slave. It receives the transmitted pulses and
reconstructs the SPI signals on its output port, as shown
in Table 3. In addition, the slave device may transmit a
return data pulse to the master to set the state of MISO.
See isoSPI Interaction and Timing for additional details.
Table 3. Slave SPI Port Output
RECEIVED PULSE SPI PORT ACTION
Long +1
Drive CS High
Long –1
Drive CS Low
Short +1
1. Set MOSI = 1
2. Pulse SCK
Short –1
1. Set MOSI = 0
2. Pulse SCK
RETURN PULSE
None
Short –1 Pulse
if MISO = 0
(No Return Pulse
if MISO = 1)
A slave LTC6820 never transmits long (CS) pulses. Fur-
thermore, a slave will only transmit a short –1 pulse (when
MISO = 0), never a +1 pulse. This allows for multiple slave
devices on a single cable without risk of collisions (see
Multidrop section).
isoSPI Pulse Specifications
Figure 2 details the timing specifications for the +1 and
–1 isoSPI pulses. The same timing specifications apply to
either version of these symmetric pulses. In the Electrical
Characteristics table, these specifications are further
separated into CS (long) and Data (short) parameters.
A valid pulse must meet the minimum spec for t1/2PW and
the maximum spec for tINV. In other words, the half-pulse
width must be long enough to pass through the appropriate
pulse timer, but short enough for the inversion to begin
within the valid window of time.
The response observed at MOSI, MISO or CS will occur
after delay tDEL from the pulse inversion.
Setting Clock Phase and Polarity (PHA and POL)
SPI devices often use one clock edge to latch data and
the other edge to shift data. This avoids timing problems
associated with clock skew. There is no standard to specify
whether the shift or latch occurs first. There is also no
requirement for data to be latched on a rising or falling
clock edge, although latching on the rising edge is most
common. The LTC6820 supports all four SPI operating
modes, as configured by the PHA and POL Pins.
Table 4. SPI Modes
MODE POL PHA
0
0
0
1
0
1
2
1
0
3
1
1
DESCRIPTION
SCK Idles Low, Latches on Rising (1st) Edge
SCK Idles Low, Latches on Falling (2nd) Edge
SCK Idles High, Latches on Falling (1st) Edge
SCK Idles High, Latches on Rising (2nd) Edge
+1 PULSE
VA
VTCMP
VIP – VIM
–VTCMP
–VA
MOSI, MISO OR CS
–1 PULSE
VA
VTCMP
VIP – VIM
–VTCMP
–VA
MOSI, MISO OR CS
t1/2PW
tINV
tINV
t1/2PW
t1/2PW
tDEL
t1/2PW
tDEL
Figure 2. isoSPI Differential Pulse Detail
6820 F02
6820f
11
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