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78Q2120C
TDK
TDK Corporation TDK
78Q2120C Datasheet PDF : 33 Pages
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78Q2120C
10/100BASE-TX Transceiver
MR17: Interrupt Control/Status Register (continued)
Bit
Symbol
Type Default Description
17.3 LP-ACK_INT RC
0 Link Partner Acknowledge Interrupt: This bit is set high by the
auto-negotiation logic when FLP bursts are received with the
acknowledge bit set.
17.2 LS_CHG_INT RC
0 Link Status Change Interrupt: This bit is set when the link
transitions from an OK status to a FAIL status.
17.1 RFAULT_INT RC
0 Remote Fault Interrupt: This bit is set when a remote fault
condition has been indicated by the link partner.
17.0
ANEG-
RC
COMP_INT
0 Auto-Negotiation Complete Interrupt: This bit is set by the auto-
negotiation logic upon successful completion of auto-negotiation.
MR18: Diagnostic Register
Bit
18.15
18.14:13
18.12
Symbol
RSVD
RSVD
ANEGF
18.11
DPLX
Type
R
R/W
RC
R
Default Description
0 Reserved
00h Reserved: Must set to ‘00h’.
0 Auto-Negotiation Fail Indication: This bit is set when auto-
negotiation completes and no common technology was found. It
remains set until read.
0 Duplex Indication: This bit indicates the result of the auto-
negotiation for duplex arbitration as follows:
0 : Half-duplex was the highest common denominator
18.10
RATE
R
1 : Full-duplex was the highest common denominator
0 Rate Indication: This bit indicates the result of the auto-negotiation
for data rate arbitration as follows:
0 : 10Base-T was the highest common denominator
18.9 RX_PASS R
18.8 RX_LOCK R
18.7:0
RSVD
R/W
1 : 100Base-TX was the highest common denominator
0 Receiver Pass Indication: In 10Base-T mode, this bit indicates that
Manchester data has been detected. In 100Base-TX mode, it
indicates that the receive signal activity has been detected (but not
necessarily locked on to).
0 Receive PLL Lock Indication: Indicates that the Receive PLL has
locked onto the receive signal for 100Base-TX operation.
00h Reserved: Must set to ‘00h’.
© 2003 TDK Semiconductor Corporation, Proprietary and Confidential
- 18 -
Rev_1.1

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