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RTL8101

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC’97 CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

RTL8101L

4-0

R

LO_LDILO

Assign the last descriptor to be run. After the last transaction has been

completed for this last descriptor, LINE-Out bus master should stop.

6.4 LINE-Out DMA Status Register

(Offset 0003h, RO)

Bit

R/W

Symbol

Description

7-2

-

-

Reserved

1

R

LO_Curr_Last Current descriptor is the last descriptor. This bit will be auto cleared

0

R

LO_LH

The LINE-Out bus master is not active or the last descriptor has finished

transaction. This bit will be auto cleared by H/W when bus master is active.

6.5 LINE-Out DMA Control Register

(Offset 0004h-0005h, R/W)

Bit

15-12

11-8

7

6-5

4

3

2

1

0

R/W

-

R/W

R/W

-

R/W

R/W

R/W

R/W

R/W

Symbol

-

LO_DMA_TH

LO_RS_DMA

-

FIFOUNIE

LO_CDIE

LO_LDIE

LO_PDMA

LO_Start

Description

Reserved

LINE-OUT DMA Threshold Control:

0,1: When FIFO is empty, DMA will be triggered.

2,3: When sample number in FIFO < 2, DMA will be triggered.

…

E,F: When sample number in FIFO < 14, DMA will be triggered.

Once LINE1-Out DMA is triggered, DMA will continuously read from

System memory until samples number in FIFO is equal to threshold.

Set to clear all registers (offset at 0000h ~ 0007h) related to DMA, and

output FIFO should be flushed. This bit is auto cleared and should be set

only when DMA is halted.

Reserved

FIFO Under-Run Interrupt Enable:

1: Enable interrupt caused by FIFO under-run.

0: Disable interrupt caused by FIFO under-run even the ‘FIFO_un’ is set.

Current Descriptor Interrupt Enable:

1: Enable interrupt caused by current descriptor has finished its transaction.

0: Disable interrupt caused by current descriptor even the ‘Curr_End’ is set.

Last Descriptor Interrupt Enable:

1: Enable interrupt caused by the last descriptor has finished its transaction.

0: Disable interrupt caused by the last descriptor even the ‘Last_End’ is set.

Pause LINE-Out DMA:

1: The LINE1-Out DMA is paused. FIFO request to PCI bus is frozen,

residual data in FIFO send to AC-LINK is also froze, whether controller

should continuously send the latest data before FIFO froze depends on

the BU setting for descriptor.

0: resume DMA

LINE-Out DMA Start/Stop:

1: Start bus master transaction, and the first descriptor assigned in

“Starting Descriptor Index”.

0: Stop bus master transaction

6.6 Residual Samples Count in Current LINE-Out Descriptor Register

2003-05-28

31

Rev.1.3

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