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RTL8101

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC’97 CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

RTL8101L

3Dh

IPR

R

0

0

0

0

0

0

0

1

3Eh MNGNT R

0

0

1

0

0

0

0

0

3Fh

MXLAT

R

0

0

1

0

0

0

0

0

40h

RESERVED(ALL 0)

|

-

FFh

8.4 PCI Power Management functions

The RTL8101L is compliant to ACPI (Rev 1.1), PCI Power Management (Rev 1.1), and Device Class Power Management

Reference Specification (V1.0a), such as to support an OS Directed Power Management (OSPM) environment. To support this,

the RTL8101L provides the following capabilities:

The RTL8101L can monitor the network for a Wakeup Frame, a Magic Packet, or a Link Change, and notify the system

via PME# when such a packet or event arrives. Then, the whole system can be restored to a working state to process the

incoming jobs.

The RTL8101L can be isolated from the PCI bus automatically with the auxiliary power circuit when the PCI bus is in B3

state, i.e. the power on the PCI bus is removed. When the motherboard includes a built-in RTL8101L single-chip fast

Ethernet controller, the RTL8101L can be disabled when needed by pulling the isolate pin low to 0V.

When the RTL8101L is in power down mode (D1 ~ D3),

♦ The Rx state machine is stopped, and the RTL8101L keeps monitoring the network for wakeup event such Magic Packet,

Wakeup Frame, and/or Link Change, in order to wake up the system. When in power down mode, the RTL8101L will not

reflect the status of any incoming packet in the ISR register and will not receive any packets into the Rx FIFO.

♦ The FIFO status and the packets which are already received into Rx FIFO before entering into power down mode, are kept

by the RTL8101L during power down mode

♦ The transmission is stopped. The action of PCI bus master mode is stopped as well. The Tx FIFO is kept.

♦ After restoration to a D0 state, the PCI bus master mode continues to transfer the data, which is not yet moved into the Tx

FIFO from the last break. The packet that was not transmitted completely last time is transmitted again.

D3cold_support_PME bit(bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI configuration space.

If 9346 D3cold_support_PME bit(bit15, PMC) = 1, the above 4 bits depend on the existence of Aux power.

If 9346 D3cold_support_PME bit(bit15, PMC) = 0, the above 4 bits are all 0's.

Ex.:

1. If 9346 D3c_support_PME = 1,

Aux. power exists, then PMC in PCI config space is the same as 9346 PMC, i.e. if 9346 PMC = C2 F7,

then PCI PMC = C2 F7.

Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above 4 bits are

all 0’s. I.e. if 9346 PMC = C2 F7, the PCI PMC = 02 76.

In this case, if wakeup support is desired when the main power is off, it is suggested that the 9346

PMC be set to: C2 F7 (RT 9346 default value). It is not recommended to set the D0_support_PME

bit to “1”.

2. If 9346 D3c_support_PME = 0,

Aux. power exists, then PMC in PCI config space is the same as 9346 PMC. I.e. if 9346 PMC = C2 77,

then PCI PMC = C2 77.

Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above 4 bits are

all 0’s. I.e. if 9346 PMC = C2 77, the PCI PMC = 02 76.

In this case, if wakeup support is not desired when the main power is off, it is suggested that the 9346

PMC to be 02 76. It is not recommended to set the D0_support_PME bit to “1”.

Link Wakeup occurs only when the following conditions are met:

♦ The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8101L is in isolation state,

or the PME# can be asserted in current power state.

2003-05-28

51

Rev.1.3

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