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RTL8101

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC’97 CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

IDSEL

I

98

INTAB

O/D

80

IRDYB

S/T/S

19

TRDYB

S/T/S

20

PAR

T/S

24

PERRB

S/T/S

25

SERRB

O/D

26

STOPB

S/T/S

23

RSTB

I

81

4.3 EEPROM Interface

Symbol

AUX/EEDI

Type

I/O

Pin No

53

EESK

O

54

EEDO

O, I

52

RTL8101L

Initialization device select: This pin allows the RTL8101L to identify

when configuration read/write transactions are intended for it.

INTAB: Used to request an interrupt. It is asserted low when an

interrupt condition occurs, as defined by the Interrupt Status, Interrupt

Mask and Interrupt Enable registers.

Initiator ready: This indicates the initiating agent’s ability to complete

the current data phase of the transaction.

As a bus master, this signal will be asserted low when the RTL8101L is

ready to complete the current data phase transaction. This signal is used in

conjunction with the TRDYB signal. Data transaction takes place at the

rising edge of CLK when both IRDYB and TRDYB are asserted low. As a

target, this signal indicates that the master has put data on the bus.

Target ready: This indicates the target agent’s ability to complete the

current phase of the transaction.

As a bus master, this signal indicates that the target is ready for the data

during write operations and with the data during read operations. As a

target, this signal will be asserted low when the (slave) device is ready to

complete the current data phase transaction. This signal is used in

conjunction with the IRDYB signal. Data transaction takes place at the

rising edge of CLK when both IRDYB and TRDYB are asserted low.

Parity: This signal indicates even parity across AD31-0 and C/BE3-0

including the PAR pin. As a master, PAR is asserted during address and

write data phases. As a target, PAR is asserted during read data phases.

Parity error: When the RTL8101L is the bus master and a parity error

is detected, the RTL8101L asserts both SERR bit in ISR and

Configuration Space command bit 8 (SERRB enable). Next, it

completes the current data burst transaction, then stops operation and

resets itself. After the host clears the system error, the RTL8101L

continues its operation.

When the RTL8101L is the bus target and a parity error is detected, the

RTL8101L asserts this PERRB pin low.

System error: If an address parity error is detected and Configuration

Space Status register bit 15 (detected parity error) is enabled,

RTL8101L asserts both SERRB pin low and bit 14 of Status register in

Configuration Space.

Stop: Indicates the current target is requesting the master to stop the

current transaction.

Reset: When RSTB is asserted low, the RTL8101L performs internal

system hardware reset. RSTB must be held for a minimum of 120 ns.

Description

1. Aux. Power Detect: This pin is used to notify the RTL8101L of the

existence of Aux. power during initial power-on or a PCI reset.

This pin should be pulled high to the Aux. power via a resistor to detect

the Aux. power. Doing so, will enable wakeup support from ACPI D3

cold or APM power-down. If this pin is not pulled high, the RTL8101L

assumes that no Aux. power exists.

2. The MA2-0 pins are switched to EESK, EEDI, EEDO in 93C46

programming or auto-load mode.

2003-05-28

7

Rev.1.3

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