RTL8208B-LF Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8208B-LF Datasheet PDF : 65 Pages
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RTL8208B-LF/RTL8208BF-LF
Datasheet
Pin Name
TX_EN[7:0]
TX_CLK/TX_EN[4]
Pin
59, 67, 75,
81, 88, 96,
102, 110
Type
I
Description
Transmit Enable.
RMII: TX_EN indicates the di-bits on TXD is valid and is
synchronous to REFCLK.
SMII: The I/O pin of TX_EN should not be used.
RXD0[7:0]
RXD1[7:0]
CRS_DV[7:0]
RX_SYNC/CRS_DV[3]
RX_CLK/CRS_DV[4]
SYNC/
TX_SYNC
55
63
71
77
84
92
98
106
54
62
70
76
83
91
97
105
56
64
72
78 (16mA)
85
93
99
07
82
O
(Pd)
(Pd)
(Pu)
(Pd)
(Pu)
(Pd)
(Pd)
(Pd)
O
(Pd)
(Pd)
(Pd)
(Pd)
(Pd)
(Pd)
(Pu)
(Pd)
O
(Pu)
(Pu)
(Pu)
(ND)
(Pu)
(Pu)
(Pd)
(Pd)
I
(Pd)
SS-SMII: TX_EN[4] of RMII is used as TX_CLK, which is a
125MHz clock input from MAC.
The I/O pin of TX_EN should not be used.
Receive Data Input (bit 0).
RMII: RXD0 and RXD1 output di-bits synchronously to REFCLK.
SMII: RXD0 outputs data or in-band management information
synchronously to REFCLK. In 100Mbps, RXD0 outputs a new 10-
bit segment starting with SYNC. In 10Mbps, RXD0 must repeat
each 10-bit segment 10 times.
SS-SMII: RXD0 behaves as SMII except synchronous to RX_CLK
instead of REFCLK and inputs a new 10-bit segment starting with
RX_SYNC instead of SYNC.
All pins driver capacity = 8mA
Receive Data Input (bit 1).
RMII: RXD1 and RXD0 output di-bits synchronously to REFCLK.
SMII/SS-SMII: The I/O pin of RXD1 should not be used.
All pins driver capacity = 8mA
Carrier Sense and Data Valid.
RMII: CRS_DV is asynchronous to REFCLK and asserts when the
medium is non-idle.
SMII: CRS_DV[7:0] are not used and driven low.
SS-SMII: CRS_DV[3] of RMII is used as RX_SYNC which is a
sync signal used to delimit the 10-bit segment of RXD0 for all ports.
CRS_DV[4] of RMII is used as RX_CLK, which is a 125MHz clock
output. CRS_DV[7:5] and CRS_DV[2:0] are not used.
All pins driver capacity = 8mA, except pin 78 (16mA).
Sync/Transmit Synchronous.
SMII: SYNC is a sync signal used to delimit a 10-bit segment of
RXD0 and TXD0 for all ports.
SS-SMII: TX_SYNC is a sync signal used to delimit the 10-bit
segment of TXD0 for all ports.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
8
Track ID: JATR-1076-21 Rev. 1.3
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