FM24C16A Ver la hoja de datos (PDF) - Ramtron International Corporation
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FM24C16A Datasheet PDF : 12 Pages
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FM24C16A
The operation is now a current address read. This
operation is illustrated in Figure 9.
By Master
Start
Address
S
Slave Address 1 A
No
Acknowledge
Data Byte
1P
Stop
By FM24C16
Acknowledge Data
Figure 7. Current Address Read
By Master
Start
Address
Acknowledge
No
Acknowledge
S
Slave Address 1 A
Data Byte
A
Data Byte
1P
By FM24C16
Acknowledge
Data
Figure 8. Sequential Read
Stop
By Master Start
Address
Start
Address
S
Slave Address 0 A
Word Address
AS
Slave Address 1 A
By FM24C16
Acknowledge
Acknowledge
No
Acknowledge
Stop
Data Byte
A
Data Byte
1P
Data
Figure 9. Selective (Random) Read
Endurance
The FM24C16A internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The FRAM
architecture is based on an array of rows and
columns. Rows are defined by A10-A3. Each access
causes an endurance cycle for a row. Endurance can
be optimized by ensuring frequently accessed data is
placed in different rows. Regardless, FRAM read and
write endurance is effectively unlimited at the 1MHz
two-wire speed. Even at 3000 accesses per second to
the same row, 10 years time will elapse before 1
trillion endurance cycles occur.
Rev 3.0
Mar. 2005
Page 7 of 12
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