LTC1064-1 Ver la hoja de datos (PDF) - Linear Technology
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LTC1064-1 Datasheet PDF : 8 Pages
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LTC1064-1
PI FU CTIO S (Pin Numbers Refer to the 14-Pin Package)
operation both pins should be tied to one half supply
(Figure 2). Also Pin 8 and Pin 10, although they are not
internally connected should be tied to analog ground or
system ground. This improves the clock feedthrough
performance.
V+, V– (Pins 4, 12): The V+ and V– pins should be
bypassed with a 0.1µF capacitor to an adequate analog
ground. Low noise, nonswitching power supplies are
recommended. To avoid latchup when the power supplies
exhibit high turn-on transients, a 1N5817 Schottky diode
should be added from the V+ and V– pins to ground
(Figure 1).
INV A, R(h, I) (Pins 7, 14): A very short connection
between Pin 14 and Pin 7 is recommended. This connec-
tion should be preferably done under the IC package. In a
breadboard, use a one inch, or less, shielded coaxial cable;
the shield should be grounded. In a PC board, use a one
inch trace or less; surround the trace by a ground plane.
NC (Pins 8, 10): The “no connection” pins preferably
should be grounded.
fCLK (Pin 11): For ±5V supplies the logic threshold level is
1.4V. For ±8V and 0V to 5V supplies the logic threshold
levels are 2.2V and 3V respectively. The logic threshold
levels vary ±100mV over the full military temperature
range. The recommended duty cycle of the input clock is
50% although for clock frequencies below 500kHz the
clock “on” time can be as low as 200ns. The maximum
clock frequency for ±5V supplies is 4MHz. For ±7V sup-
plies and above, the maximum clock frequency is 5MHz.
Do not allow the clock levels to exceed the power supplies.
For clock level shifting (see Figure 3).
TYPICAL APPLICATIO S
V+
1N5817
VIN
0.1µF
1
14
INV C R(h, I)
2
VIN
COMP2* 13
3
AGND
V– 12
4
LTC1064-1
V+
fCLK
11
5
AGND
NC 10
6
COMP1*
7
INV A
9
VOUT
NC 8
1N5817
VOUT
V–
0.1µF
1064 F01
Figure 1. Using Schottky Diodes to Protect
the IC from Power Supply Spikes
VIN
V+
5k
0.1µF
5k
1
INV C
R(h, I) 14
2
VIN
COMP2* 13
3
AGND
V– 12
4
LTC1064-1
V+
fCLK
11
5
AGND
NC 10
6
COMP1*
VOUT 9
7
INV A
NC 8
V+
2.2k
5k 1µF
T2L
LEVEL
VOUT
1064 F03
Figure 3. Level Shifting the Input T2L Clock
for Single Supply Operation, V+ >6V.
V+= 15V
1
INV C
R(h, I) 14
VIN
0.1µF
5k
2
VIN
13
COMP2*
3
AGND
V– 12
4
LTC1064-1
V+
fCLK
11
5
AGND
NC 10
0.1µF
6
9
V+/2
COMP1* VOUT
5k
7
INV A
8
NC
0V TO 10V
VOUT
1064 F02
Figure 2. Single Supply Operation. If Fast Power Up
or Down Transients are Expected, Use a 1N5817
Schottky Diode Between Pin 4 and Pin 5.
VIN
0.1µF
1
INV C
R(h, I) 14
2
VIN
13
COMP2*
3
AGND
V– 12
4
LTC1064-1
V+
fCLK
11
5
AGND
10
NC
6
COMP1*
7 INV A
9
VOUT
8
NC
RECOMMENDED OP AMPS:
LT1022, LT318, LT1056
POWER SOURCE
V+
V–
0.1µF
10k
0.1µF
10k
–
+
0.1µF
VOUT
1064 F04
Figure 4. Buffering the Filter Output. The Buffer Op Amp
Should Not Share the LTC1064-1 Power Lines.
10641fa
5
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