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ML4801

Variable Feedforward PFC/PWM Controller Combo

Fairchild Semiconductor 

ML4801

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques

employ trailing edge modulation in which the switch will

turn on right after the trailing edge of the system clock.

The error amplifier output voltage is then compared with

the modulating ramp. When the modulating ramp reaches

the level of the error amplifier output voltage, the switch

will be turned OFF. When the switch is ON, the inductor

current will ramp up. The effective duty cycle of the

trailing edge modulation is determined during the ON

time of the switch. Figure 3 shows a typical trailing edge

control scheme.

In the case of leading edge modulation, the switch is

turned OFF right at the leading edge of the system clock.

When the modulating ramp reaches the level of the error

amplifier output voltage, the switch will be turned ON.

The effective duty-cycle of the leading edge modulation

is determined during the OFF time of the switch. Figure 4

shows a leading edge control scheme.

One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to

minimize the momentary “no-load” period, thus lowering

ripple voltage generated by the switching action. With

such synchronized switching, the ripple voltage of the

first stage is reduced. Calculation and evaluation have

shown that the 120Hz component of the PFC’s output

ripple voltage can be reduced by as much as 30% using

this method.

TYPICAL APPLICATIONS

Figure 9 is the application circuit for a complete 100W

power factor corrected power supply, designed using the

methods and general topology detailed in Application

Note 33.

L1

I1

+

VIN

DC

SW2 I2 I3

SW1

I4

RL

C1

REF +–EAU3

RAMP

OSC

+

– U1

CLK

U4

DFF

RQ

D U2

Q

CLK

RAMP

VEAO

VSW1

TIME

TIME

L1 SW2 I2

I3

I1

+

I4

VIN

DC

SW1

RL

C1

+–EAU3

REF

RAMP

OSC

CLK

U4

VEAO

+ CMP

– U1

DFF

RQ

D U2

Q

CLK

RAMP

VEAO

VSW1

TIME

TIME

Figure 3. Typical Trailing Edge Control Scheme

Figure 4. Leading/Trailing Edge Control Scheme

10

REV. 1.1 3/9/2001

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