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LF4415

Video Memory / FIFO

LUXPIA 

PRELIMINARY

LF4460

LF4430

LF4415

Video Memory / FIFO

Configuration Register Definitions

FRAME

MEMORY

Register 9

Detect & Use

Embedded TRS

Pre-amble

Register 9 [7:6] = TRS_DETECT[1:0] - Detect & Act on Embedded TRS EAV (a)

00

disable auto-TRS sync detection (DEFAULT)

01

V-bit of embedded TRS EAV CLEARs current write pointer. See Register 9[5:4].

10

F-bit of embedded TRS EAV SETs current write pointer to value set by ADDR

11

F-bit of embedded TRS EAV CLEARs current write pointer. See Register 9[5:4].

TRS Trigger

Control

Register 9 [5] = TRS_TRIGGER _B - TRS Trigger Control, Chnl B (ONLY for DUAL-CHANNEL)

0

use only falling F/V bit in TRS - FRAME SYNC; otherwise ignore (DEFAULT)

1

use both rising and falling F/V bits in TRS

Register 9 [4] = TRS_TRIGGER - TRS Trigger Control, Chnl A

0

use only falling F-bit in EAV - FRAME SYNC; otherwise ignore (DEFAULT)

1

use both rising and falling F-bit in EAV - FIELD SYNC

Register A

Write/Read

Pointer Trigger

Control

Register 9 [3:0] = Reserved [LOAD ‘0000’ IF MODIFYING REG 9]

Register A [7:6] = Reserved [LOAD ‘00’ IF MODIFYING REG A]

Register A [5:0] PTR_CNTRL - Individual W/R Pointer Trigger Control

A [5] RSET

0 = Falling edge triggered (DEFAULT ), 1 = Active LOW

A [4] RCLR

0 = Falling edge triggered (DEFAULT ), 1 = Active LOW

A [3] BSET

0 = Falling edge triggered (DEFAULT ), 1 = Active LOW

A [2] BCLR

0 = Falling edge triggered (DEFAULT ), 1 = Active LOW

A [1] ASET

0 = Falling edge triggered (DEFAULT ), 1 = Active LOW

A [0] ACLR

0 = Falling edge triggered (DEFAULT ), 1 = Active LOW

Trigger Control bit = 0: Each falling edge on the corresponding control pin (control signal must still

fall within setup/hold spec to associated CLK) overrides memory address counter for exactly one clock

cycle, after which normal memory address incrementing immediately resumes.

Trigger Control bit = 1: The corresponding ‘active LOW’ control pin continuously overrides the memory

address counter as long as it is held LOW. Memory address incrementing resumes when the pin is

returned HIGH.

NOTE: In Single-Channel modes (MODE=x0xx), the following trigger control pairs must be set the

same: WSET0 / WSET1 along with WCLR0 / WCLR0.

LOGIC Devices Incorporated

www.logicdevices.com

19

High Performance Memory Product

January 23, 2008 LDS-44xx-A

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