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LPC47N237-MD

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC -> Microchip 

3.3v I/O Controller for Port Replicators and Docking Stations

Chapter 6 Power/Clock Functionality

The LPC47N237 has two power planes: VCC and VTR. It contains 24 MHz crystal pins and 24 MHz clock

output.

6.1

3.3 Volt Operation / 5 Volt Tolerance

The LPC47N237 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V

tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling.

These pins are:

ƒ LAD[3:0]

ƒ nLFRAME

ƒ nLDRQ

ƒ nLPCPD

The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following

pins:

ƒ nPCI_RESET

ƒ PCI_CLK

ƒ SER_IRQ

ƒ nCLKRUN

ƒ nIO_PME

6.2

VCC Power

The LPC47N237 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational

Description Section and the Maximum Current Values subsection.

6.3

VTR Power

The LPC47N237 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up

events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the

Operational Description Section. The maximum VTR current that is required depends on the functions that

are used in the part. See Trickle Power Functionality subsection and the Maximum Current Values

subsection. If the LPC47N237 is not intended to provide wake-up capabilities on standby current, VTR can

be connected to VCC. The VTR pin generates a VTR Power-on-Reset signal to initialize these components.

Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full

minimum potential at least 10 µs before VCC begins a power-on cycle. When VTR and VCC are fully

powered, the potential difference between the two supplies must not exceed 500mV.

SMSC DS – LPC47N237

Page 21

DATASHEET

Revision 0.3 (10-26-04)

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