M12L64164A-6BG2Y Ver la hoja de datos (PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L64164A-6BG2Y

1M x 16 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M12L64164A

DC CHARACTERISTICS

Recommended operating condition unless otherwise noted，TA = 0 to 70 °C

PARAMETER

SYMBOL

TEST CONDITION

VERSION

-5 -6 -7

Operating Current

(One Bank Active)

ICC1

Precharge Standby Current ICC2P

in power-down mode

ICC2PS

Burst Length = 1, tRC ≥ tRC(min), IOL = 0 mA,

tcc = tcc(min)

CKE ≤ VIL(max), tcc = tcc(min)

CKE & CLK ≤ VIL(max), tcc = ∞

100 85 85

2

1

ICC2N

CKE ≥ VIH(min), CS ≥ VIH(min), tcc = tcc(min)

20

Input signals are changed one time during 2CLK

Precharge Standby Current

in non power-down mode

ICC2NS

CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞

input signals are stable

10

Active Standby Current

ICC3P

CKE ≤ VIL(max), tcc = tcc(min)

10

in power-down mode

ICC3PS

CKE & CLK ≤ VIL(max), tcc = ∞

10

CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns

Active Standby Current

ICC3N

Input signals are changed one time during 2clks

30

in non power-down mode

All other pins ≥ VDD-0.2V or ≤ 0.2V

(One Bank Active)

ICC3NS

CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞

input signals are stable

25

Operating Current

(Burst Mode)

Refresh Current

Self Refresh Current

ICC4

IOL = 0 mA, Page Burst, All Bank active

Burst Length = 4, CAS Latency = 3

ICC5

tRFC ≥ tRFC(min), tCC = tcc(min)

ICC6

CKE ≤ 0.2V

180 150 140

180 150 140

1

UNIT NOTE

mA

1,2

mA

mA

mA

mA

mA

mA 1,2

mA

mA

Note : 1. Measured with outputs open.

2. Input signals are changed one time during 2 CLKS.

Elite Semiconductor Memory Technology Inc.

Publication Date: May 2009

Revision: 3.4

4/45

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