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RT9231A

Advanced PWM and Triple Linear Power Controller

Richtek Technology 

RT9231A

Functional Pin Description

DRIVE2 (Pin 1)

Connect this pin to the gate of an external MOSEFT.

This pin provides the drive for the AGP regulator’s

pass transistor.

FIX (Pin 2)

Grounding this pin bypasses the internal resistor

dividers that set the voltage of the 1.5V and 1.8V linear

regulators. This way, the output voltage of the two

regulators can be adjusted from 1.3V up to the input

voltage (+3.3V or +5V) by way of an external resistor

divider corrected at the corresponding VSEN pin. The

new output voltage set by the external resistor divider

can be determined using the following formula:

VOUT = 1.265V x (1+

ROUT )

RGND

Where ROUT is the resistor connected from VSEN to

the output of the regulator, and RGND is the resistor

connected from VSEN to ground. Left open, this pin is

pulled high enabling fixed output voltage operation.

VID0, VID1, VID2, VID3, VID4 (Pin 7, 6, 5, 4, and 3)

VID0-4 are TTL-compatible the input pins to the 5-bit

DAC. The state logic of these five pins program the

internal voltage reference, DACOUT. The level of

DACOUT sets the microprocessor core converter

output voltage, as well as the corresponding PGOOD

and OVP thresholds. Table 1 specifies the DACOUT

voltage of 32 combinations of VID levels.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate

the status of the PWM converter output voltage. This

pin is pulled low when the synchronous regulator

output is not within ±10% of the DACOUT reference

voltage, or when any of the other outputs are below

their under-voltage thresholds.

SD (Pin 9)

This pin shuts down the entire IC. A TTL-compatible,

logic level high signal applied at this pin immediately

disables all outputs. When re-enabled, the IC

undergoes a new soft-start cycle. Left open, this pin is

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pulled low by an internal pull-down current source,

enabling operation.

VSEN2 (Pin 10)

Connect this pin to the output of the AGP linear

regulator. The voltage at this pin is regulated to the

level pre-determined by the logic-level status of the

SELECT pin. This pin is also monitored for under-

voltage events.

SELECT (Pin 11)

This pin determines the output voltage of the AGP bus

switching regulator. A low TTL input sets the output

voltage to 1.5V while a high input sets the output

voltage to 3.6V. When the input voltage is 3.3V,

DRIVE2 continuously turn on providing a DC current

path from the input(+3.3VIN ) to output (VOUT2 ) of the

AGP controller.

SS (Pin 12)

Connect a capacitor from this pin to ground. This

capacitor, along with an internal 28µA (VSS>1V)

current source, sets the soft-start interval of the

converter.

FAULT (Pin 13)

This pin is low during normal operation, but it is pulled

to 8V (VCC = 12V) in the event of an over-voltage or

over-current condition.

VSEN4 (Pin 14)

Connect this pin to the output of the 1.8V regulator.

This pin is monitored for under-voltage events.

DRIVE4 (Pin 15)

Connect this pin to the gate of an external MOSEFT.

This pin provides the drive for the 1.8V regulator’s

pass transistor.

VAUX (Pin 16)

This pin provides boost current for the two linear

regulator output drives in the event bipolar NPN

DS9231A-02 July 2001

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