PI5A4599A
SOTINY Low Resistance,
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Test Circuits/Timing Diagrams
Switch
Input
+3V*
Logic
Input
V+
V+
NO
COM
or NC
RL
IN
1kΩ
GND
VOUT
CL
35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE
( ) VOUT = VNO
RL
RL + RON
Logic +3V
Input 0V
Switch
Output 0V
50%
VOUT 90%
tON
tr <20ns
tf <20ns
tOFF
90%
LOGIC INPUT WAVEFORMS INVERTED FOR
SWITCHES THAT HAVE OPPOSITE LOGIC
* 1.5V FOR 3.3V SUPPLY
Figure 1. Switching Time
+5V
VGEN
Logic
Input
COM
.1µF
V+
NO or
NC
IN
GND
VOUT
CL
0.22nF
VOUT
IN
OFF
OFF
IN
Figure 2. Charge Injection
ON
ON
Q = (∆VOUT)(CL)
∆VOUT
OFF
OFF
+3V
Logic
Input
V+
V+
NC
COM
NO
IN
GND
VOUT
RL
CL
1kΩ
35pF
Logic +3V
Input 0
Switch
Output
(VOUT)
CL INCLUDES FIXTURE AND STRAY CAPACITANCE
50%
0.9xVOUT
tBBM
0.9xVOUT
Figure 3. Break-Before-Make Interval
6
PS8553 08/10/01