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74LVTH16500

Low Voltage 18-Bit Universal Bus Transceivers with 3-STATE Outputs (Preliminary)

Fairchild Semiconductor 

Preliminary

Connection Diagram

Functional Description

For A-to-B data flow, the device operates in the transparent

mode when LEAB is HIGH. When LEAB is LOW, the A

data is latched if CLKAB is held at a HIGH or LOW logic

level. If LEAB is LOW, the A bus data is stored in the latch/

flip-flop on the HIGH-to-LOW transition of CLKAB. Output-

enable OEAB is active-HIGH. When OEAB is HIGH, the

Logic Diagram

Pin Descriptions

Pin Names

Description

A1–A18

Data Register A Inputs/3-STATE Outputs

B1–B18

Data Register B Inputs/3-STATE Outputs

CLKAB, CLKBA Clock Pulse Inputs

LEAB, LEBA Latch Enable Inputs

OEAB, OEBA Output Enable Inputs

Function Table (Note 1)

Inputs

OEAB LEAB CLKAB

A

Output

B

L

X

X

X

Z

H

H

X

L

L

H

H

X

H

H

H

L

↓

L

L

H

L

↓

H

H

H

L

H

X

B0 (Note 2)

H

L

L

X

B0 (Note 3)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

↓ = HIGH-to-LOW Clock Transition

Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,

LEBA, and CLKBA.

Note 2: Output level before the indicated steady-state input conditions

were established.

Note 3: Output level before the indicated steady-state input conditions

were established, provided that CLKAB was LOW before LEAB went LOW.

outputs are active. When OEAB is LOW, the outputs are in

the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

plementary (OEAB is active-HIGH and OEBA is active-

LOW).

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