CY7C4261V(2003) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Lista de partido

CY7C4261V
(Rev.:2003)

16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

First Data Word Latency after Reset with Read and Write

WCLK

D0 –D8

WEN1

tDS

tENS

D0(FIRST VALID WRITE)

D1

tFRL [17]

WEN2

(if applicable)

RCLK

EF

tSKEW1

tREF

REN1,

REN2

Q0 –Q8

OE

tOLZ

tOE

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

D2

D3

D4

tA

tA [18]

D0

D1

Notes:

17. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.

The Latency Timing applies only at the Empty Boundary (EF = LOW).

18. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06013 Rev. *A

Page 10 of 16

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