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L9826_02

Octal Low-Side Driver for resistive and inductive loads with serial/parallel input control, output protection and diagnostic

STMicroelectronics 

Figure 1. Timing of the Serial Interface.

NCS

tsclch thclcl

tclh

tcll

CLK

tcsdv

tpcld

SDO

not defined

tscld

D8

thcld

SDI

D8

D7

L9826

tsclcl

thclch

tpchdz

D1

D1

The SPI register data are transferred to the output latch at rising NCS edge. The digital filter between NCS and

the output latch ensures that the data are transferred only after 8 CLK cycles or multiple of 8 CLK cycles since

the last NCS falling edge. The NCS changes only at low CLK.

Outputs Control Tables :

Outputs 1, 2:

NON1, 2

1

0

0

1

SPI-bit 1, 2

0

0

1

1

Output 1, 2

off

on

on

on

Outputs 3 to 8:

SPI-bit 3 ... 8

Output 3 ... 8

0

1

off

on

Figure 2. Output Control register structure

MSB

LSB

Q2 Q4 Q6 Q8 Q1 Q3 Q5 Q7

Control-bit output 7

Control-bit output 5

Control-bit output 3

Control-bit output 1

Control-bit output 8

Control-bit output 6

Control-bit output 4

Control-bit output 2

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