AV9148F-10 Ver la hoja de datos (PDF) - Integrated Circuit Systems
Número de pieza
componentes Descripción
Lista de partido
AV9148F-10 Datasheet PDF : 12 Pages
| |||
ICS9148-10
Pin Descriptions
PIN NUMBER
1, 2, 47
3
4
5
6, 12, 18
7
8, 10, 11, 13, 14, 16, 17
9, 15
19, 33
20, 32
21
22, 23
24
25
26, 27
28
29
30
31
37, 41
34, 38
35, 36, 39, 40
42
43
44, 45
46
PIN NAME
REF (0:2)
GND1
X1
X2
GND2
PCICLK_F
PCICLK (0:6)
VDD2
VDD
GND
VDD3
48MHz (0:1)
GND3
SEL100/66.6#
FS (0:1)
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
VDDL2
GNDL2
CPUCLK (3:0)
N/C
GNDL1
IOAPIC (0:1)
VDDL1
TYPE
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
PWR
IN
IN
IN
IN
IN
IN
PWR
PWR
OUT
-
PWR
OUT
PWR
DESCRIPTION
14.318MHz clock output
Ground for REF outputs
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Isolated power for core, nominally 3.3V
Isolated ground for core
Power for 48MHz outputs, nominally 3.3V
48MHz outputs
Ground for 48MHz outputs
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
Frequency Select pins
Enables Spread Spectrum feature when LOW
Powers down chip, active low
Halts CPU clocks at logic "0" level when low
Halts PCI Bus at logic "0" level when low
Power for CPU outputs, nominally 2.5V
Ground for CPU outputs.
CPU and Host clock outputs @ 2.5V
Not internally connected
Ground for IOAPIC outputs
IOAPIC outputs (14.318MHz) @ 2.5V
Power for IOAPIC outputs, nominally 2.5V
Select Functions
Functionality
Tristate
Testmode
Spread Spectrum
CPU
HI - Z
TCLK/21
Modulated2
PCI,
PCI_F
HI - Z
TCLK/61
Modulated2
REF
HI - Z
TCLK1
14.318MHz
IOAPIC
HI - Z
TCLK1
14.318MHz
48 MHz
Selection
HI - Z
TCLK/21
48.0MHz
SEL 100/66# FS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FS0
Function
0
Tri-State
1
(Reserved)
0
(Reserved)
1
Active 66.6MHz CPU, 33.3 PCI
0
Test Mode
1
(Reserved)
0
(Reserved)
1
Active 100MHz CPU, 33.3 PCI
Notes:
1. TCLK is a test clock driven on the X1 (crystal in
pin) input during test mode.
2. -1% modulation down spread from the selected
frequency.
2
Share Link: 