BR24C01A-W Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR24C01A-W Datasheet PDF : 13 Pages
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Memory ICs
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(11) Sequential read cycle (For a current read)
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
T
R
A
E
R
SLAVE
A
T
ADDRESS D
DATA(n)
S
T
O
DATA(n+x)
P
SDA
LINE
1 0 1 0 A2 A1 A0
D7
D0
D7
D0
RA
A
A
A
/C
C
C
C
WK
K
K
K
Fig.16
BR24C02-W / F-W / FJ-W / FV-W
S
T
R
A
E
R
SLAVE
A
T
ADDRESS D
DATA(n)
S
T
O
DATA(n+x)
P
SDA
LINE
1 0 1 0 A2 A1 A0
D7
D0
D7
D0
RA
A
A
A
/C
C
C
C
WK
K
K
K
Fig.17
BR24C04-W / F-W / FJ-W / FV-W
S
T
R
A
E
R
SLAVE
A
T
ADDRESS D
DATA(n)
S
T
O
DATA(n+x)
P
SDA
LINE
1 0 1 0 A2 A1PS
D7
D0
D7
D0
RA
A
A
A
/C
C
C
C
WK
K
K
K
Fig.18
• When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next
word address data can be read. [All words can be read]
• This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) using the SCL signal HIGH.
• Sequential reading can also be done with a random read.
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