RD28F1602C3B110_03 Ver la hoja de datos (PDF) - Intel

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RD28F1602C3B110_03

3 Volt Intel® Advanced+ Boot Block Flash Memory(C3) Stacked-Chip Scale Package Family

Intel 

3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family

program and erase operations, including verification, thereby unburdening the microprocessor or

microcontroller. The flash’s status register indicates the status of the WSM by signifying block

erase or word program completion and status.

Flash program and erase automation allows program and erase operations to be executed using an

industry-standard two-write command sequence to the CUI. Program operations are performed in

word increments. Erase operations erase all locations within a block simultaneously. Both program

and erase operations can be suspended by the system software in order to read from any other flash

block. In addition, data can be programmed to another flash block during an erase suspend.

The C3 Stacked-CSP memory device offers two low-power savings features: Automatic Power

Savings (APS) for flash memory and standby mode for flash and SRAM. The device automatically

enters APS mode following the completion of a read cycle from the flash memory. Standby mode

is initiated when the system deselects the device by driving F-CE# and S-CS1# or

S-CS2 inactive. Power savings features significantly reduce power consumption.

The flash memory can be reset by lowering F-RP# to GND. This provides CPU-memory reset

synchronization and additional protection against bus noise that may occur during system reset and

power-up/-down sequences.

1.3

Package Ballout

72 -

Figure 1. 66-Ball Stacked Chip Scale Package

1

A

NC

B

C

D

E

F

G

H

NC

234567

8 9 10 11 12

A20 A11 A15 A14 A13 A12 F-VSS F-VCCQ

NC

A16 A8 A10 A9 DQ15 S-WE# DQ14 DQ7

F-WE# NC A21

DQ13 DQ6 DQ4 DQ5

S-VSS F-RP# A22

DQ12 S-CS2 S-VCC F-VCC

F-WP# F-V

PP

A19

DQ11

DQ10 DQ2 DQ3

S-LB# S-UB# S-OE#

DQ9 DQ8 DQ0 DQ1

A18 A17 A7 A6 A3 A2

A1 S-CS1#

NC A5 A4 A0 F-CE# F-VSS F-OE# NC

NC

Top View, Balls Down

NOTES:

1. Flash upgrade balls are shown up to A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash and SRAM

combinations, 66 balls are populated on lower density devices. (Upper address balls are not populated). Ball

location A10 is “NC” on 16/2 devices only.

8

Datasheet

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