XRD66L92 Ver la hoja de datos (PDF) - Exar Corporation

Número de pieza

componentes Descripción

Lista de partido

XRD66L92

Low Voltage CMOS 12-Bit High Speed Analog-to-Digital Converter with Serial Logic Interface Port

Exar Corporation 

XRD66L92

CLK

PLOAD

Time = N

N-3 DATA VALID

Sampling

DATA N

CLK

PLOAD

Time = N

N-3 DATA VALID

tCP

tSC

SCLK

tSD

SDO

DB11 DB10

DB1 DB0 Trailing Zeroes

Sample N –3 Data

Note: Avoid SCLK and CLK Clock Edges Being Coincident

tS

tDS

SDO

DB11

DB11 available on falling edge of PLOAD

Figure 4. Serial Port Timing Chart

PHASE = 1

APERTURE: Aperture Delay Sync (output)

This signal is high when the internal sample/hold function is

sampling VIN, and goes low when it is in the hold mode (when the

ADC is comparing the stored input value to the reference lad-

der). The value of VIN at the high to low transition of APERTURE

is the value that will be digitized. A system can monitor this sig-

nal and adjust the CLK phase to accurately synchronize the

sampling point to an external event.

MINV

LINV

VRT

VIN

mid

scale

VRB

0

0

111 . . . 11

111 . . . 10

0

1

100 . . . 00

100 . . . 01

1

0

011 . . . 11

011 . . . 10

100 . . . 01

100 . . . 00

011 . . . 11

111 . . . 10

111 . . . 11

000 . . . 00

000 . . . 01

000 . . . 00

111 . . . 11

000 . . . 01

000 . . . 00

011 . . . 10

011 . . . 11

100 . . . 01

100 . . . 00

binary

inverted

2’s complement

2’s complement

Table 1. Output Data Format Truth Table

1

1

000 . . . 00

000 . . . 01

011 . . . 10

011 . . . 11

100 . . . 00

111 . . . 10

111 . . . 11

inverted

binary

MINV & LINV: Digital Output Format (inputs)

be inverted. The OFW and UFW bits are not affected by these

signals.

These signals control the format of the digital output data bits

DB0 – DB11. Normally both pins are held low so the data is in

straight binary format (all 0’s when VIN=VRB; all 1’s when

VIN=VRT). If MINV is pulled high then the MSB (DB11) will be

inverted. If LINV is pulled high then the LSBs (DB0 – DB10) will

Rev. 1.00

MINV & LINV are meant to be static digital signals. If they are

to change during operation they should only change when the

CLK is low. Changing MINV and/or LINV when CLK is high is

acceptable, but the effects on the digital outputs will not be seen

until the output latch of the output register is enabled. MINV and

7

Share Link: