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74AC373_97

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

STMicroelectronics 

74AC373

OCTAL D-TYPE LATCH

WITH 3 STATE OUTPUT NON INVERTING

s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 8 µA (MAX.) at TA = 25 oC

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s 50Ω TRANSMISSION LINE DRIVING

CAPABILITY

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 24 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC (OPR) = 2V to 6V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 373

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The AC373 is an advanced high-speed CMOS

OCTAL D-TYPE LATCH with 3 STATE OUTPUT

NON INVERTING fabricated with sub-micron

silicon gate and double-layer metal wiring C2MOS

technology. It is ideal for low power applications

mantaining high speed operation similar to

equivalent Bipolar Schottky TTL.

These 8 bit D-Type latch are controlled by a latch

enable input (LE) and an output enable input

PIN CONNECTION AND IEC LOGIC SYMBOLS

B

M

(Plastic Package)

(Micro Package)

ORDER CODES :

74AC373B

74AC373M

(OE).

While the LE inputs is held at a high level, the Q

outputs will follow the data input precisely or

inversely. When the LE is taken low, the Q

outputs will be latched precisely or inversely at

the logic level of D input data. While the (OE)

input is low, the 8 outputs will be in a normal logic

state (high or low logic level) and while high level

the outputs will be in a high impedance state.

This device is designed to interface directly High

Speed CMOS systems with TTL and NMOS

components.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

April 1997

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