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AFBR-5803Z

FDDI, 100 Mb/s ATM, and Fast Ethernet Transceivers in Low-Cost 1 × 9 Package Style

Broadcom Corporation 

AFBR-5803Z/5803TZ/5803AZ/5803ATZ

Data Sheet

Receiver Optical and Electrical Characteristics

(AFBR-5803Z/AFBR-5803TZ: TA = 0°C to +70°C, VCC = 3.135V to 3.5V or 4.75V to 5.25V.)

(AFBR-5803AZ/AFBR-5803ATZ: TA = –10°C to +85°C, VCC = 3.135V to 3.5V or 4.75V to 5.25V.)

Parameter

Symbol

Min.

Typ.

Max.

Unit Figure Note

Input Optical Power Minimum at Window Edge

Input Optical Power Minimum at Eye Center

Input Optical Power Maximum

Operating Wavelength

Duty Cycle Distortion Contributed by the Receiver

PIN Min. (W)

PIN Min. (C)

PIN Max.



DCD

—

—

–14

1270

—

–33.9

–35.2

—

—

—

–31

dBm avg. 14

a

–31.8

dBm avg. 14

b

—

dBm avg.

a

1380

nm

0.4

ns p-p

c

Data Dependent Jitter Contributed by the Receiver

DDJ

—

—

1.0

ns p-p

d

Random Jitter Contributed by the Receiver

RJ

—

—

2.14

ns p-p

e

Signal Detect – Asserted

Signal Detect – Deasserted

Signal Detect – Hysteresis

Signal Detect Assert Time (off to on)

Signal Detect Deassert Time (on to off )

PA

PD + 1.5 dB

—

PD

–45

—

PA – PD

1.5

—

AS_Max

0

2

ANS_Max

0

8

–33

dBm avg. 15

f, g

—

dBm avg. 15

h, i

—

dB

15

100

μs

15

f, g

350

μs

15

h, i

a. This specification is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal characteristics are present

per the following definitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to the maximum level is the range

over which the receiver is guaranteed to provide output data with a Bit Error Ratio (BER) better than or equal to 2.5 × 10–10.

— At the Beginning of Life (BOL)

— Over the specified operating temperature and voltage ranges

— Input symbol pattern is the FDDI test pattern defined in FDDI PMD Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle baseline wander

effect of 50 kHz. This sequence causes a near worst-case condition for inter-symbol interference.

— Receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. This worst-case window time-width is the minimum allowed

eye-opening presented to the FDDI PHY PM. Data indication input (PHY input) per the example in FDDI PMD Annex E. This minimum window time-width of

2.13 ns is based upon the worst-case FDDI PMD Active Input Interface optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns) and RJ (0.76 ns) presented

to the receiver.

To test a receiver with the worst case FDDI PMD Active Input jitter condition requires exacting control over DCD, DDJ, and RJ jitter components that is difficult

to implement with production test equipment. The receiver can be equivalently tested to the worst-case FDDI PMD input jitter conditions and meet the

minimum output data window time-width of 2.13 ns. This is accomplished by using a nearly ideal input optical signal (no DCD, insignificant DDJ and RJ) and

measuring for a wider window time-width of 4.6 ns. This is possible due to the cumulative effect of jitter components through their superposition (DCD and

DDJ are directly additive and RJ components are rms additive). Specifically, when a nearly ideal input optical test signal is used and the maximum receiver

peak-to-peak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum window time-width becomes 8.0 ns – 0.4 ns – 1.0 ns – 2.14 ns

= 4.46 ns, or conservatively 4.6 ns. This wider window time-width of 4.6 ns guarantees the FDDI PMD Annex E minimum window time-width of 2.13 ns under

worst-case input jitter conditions to the Broadcom receiver.

— Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5-MHz square-wave), input signal to simulate any cross-talk present between the

transmitter and receiver sections of the transceiver.

b. All conditions of Note a apply except that the measurement is made at the center of the symbol with no window time-width.

c. Duty Cycle Distortion contributed by the receiver is measured at the 50% threshold using an IDLE Line State, 125 MBd (62.5-MHz square-wave), input signal.

The input optical power level is –20 dBm average. See Transceiver Jitter Performance for further information.

d. Data Dependent Jitter contributed by the receiver is specified with the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The input optical power

level is –20 dBm average. See Transceiver Jitter Performance for further information.

e. Random Jitter contributed by the receiver is specified with an IDLE Line State, 125 MBd (62.5-MHz square-wave), input signal. The input optical power level

is at maximum “PIN Min. (W)”. See Transceiver Jitter Performance for further information.

f. This value is measured during the transition from low to high levels of input optical power.

g. The Signal Detect output shall be asserted within 100 μs after a step increase of the Input Optical Power. The step will be from a low Input Optical Power,

–45 dBm, into the range between greater than PA, and –14 dBm. The BER of the receiver output will be 10–2 or better during the time, LS_Max (15 μs) after

Signal Detect has been asserted. See Figure 15 for more information.

h. This value is measured during the transition from high to low levels of input optical power. The maximum value will occur when the input optical power is

either –45 dBm average or when the input optical power yields a BER of 10–2 or larger, whichever power is higher.

Broadcom

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