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CS5342_06

105 dB, 192 kHz, Multi-bit Audio A/D Converter

Cirrus Logic 

CS5342

4.4 Power-Up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and

configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies

drop below the minimum specified operating voltages to prevent power-glitch-related issues.

4.5 Analog Connections

The analog modulator samples the input at 6.144 MHz. The digital filter rejects signals within the stopband

of the filter. However, there is no rejection for input signals that are multiples of the input sampling frequency

(n × 6.144 MHz), where n=0, 1, 2, .... Figure 21 shows the suggested filter that attenuates any noise energy

at 6.144 MHz and provides the optimum source impedance for the modulators. The use of capacitors that

have a large voltage coefficient (such as general-purpose ceramics) must be avoided because these can

degrade signal linearity.

VA

100 kΩ

4.7 µF

AINx

100 kΩ

634 Ω

470 pF

C0G

91 Ω

2700 pF

CS5342 AINx

Figure 21. CS5342 Recommended Analog Input Buffer

4.6 Grounding and Power Supply Decoupling

As with any high-resolution converter, the CS5342 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 17 shows the recommended power ar-

rangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run

from the system logic supply or powered from the analog supply via a resistor. In this case, no additional

devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with

the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from

the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decou-

pling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and

REF_GND. The CDB5342 evaluation board demonstrates the optimum layout and power supply arrange-

ments. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.

4.7 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To

ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342’s in the system.

4.8 Capacitor Size on the Reference Pin (FILT+)

The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this

decoupling capacitor affects the low frequency distortion performance, as shown in Figure 22, with larger

capacitor values used to optimize low frequency distortion performance. The THD+N curves in Figure 22

DS608F1

17

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