RTL8192SE
Datasheet
2. Features
General
MAC Features
68-pin QFN
CMOS MAC, Baseband MIMO PHY, and
RF in a single chip for IEEE 802.11b/g/n
compatible WLAN
Frame aggregation for increased MAC
efficiency (A-MSDU, A-MPDU)
Low latency immediate High-Throughput
Block Acknowledgement (HT-BA)
Complete 802.11n MIMO solution for
2.4GHz band
Long NAV for media reservation with
CF-End for NAV release
2x2 MIMO technology for extended
reception robustness and exceptional
throughput
Maximum PHY data rate up to 144.4Mbps
using 20MHz bandwidth, 300Mbps using
40MHz bandwidth
Compatible with 802.11n draft 2.0
specification
Backward compatible with 802.11b/g
devices while operating at 802.11n data rates
PHY-level spoofing to enhance legacy
compatibility
MIMO power saving mechanism
Channel management and co-existence
Multiple BSSID feature allows the
RTL8192SE to assume multiple MAC
identities when used as a wireless bridge
Supports Wake-On-WLAN via Magic
Packet and Wake-up frame
Host Interface
Complies with PCI Express Base
Specification Revision 1.1
Standards Supported
IEEE 802.11e QoS Enhancement (WMM,
WMM-SA Client mode)
Transmit Opportunity (TXOP) Short
Inter-Frame Space (SIFS) bursting for higher
multimedia bandwidth
Peripheral Interfaces
General Purpose Input/Output (8 pins)
4-wire EEPROM control interface (93C46)
IEEE 802.11h TPC, Spectrum Measurement
Two configurable LED pins
IEEE 802.11k Radio Resource Measurement
IEEE 802.11i (WPA, WPA2). Open, shared
key, and pair-wise key authentication
services
Cisco Compatible Extensions (CCX) for
WLAN devices
Configurable Bluetooth Coexistence
Interface
PHY Features
IEEE 802.11n draft 2.0 MIMO OFDM
Two Transmit and Two Receive path (2T2R)
Single-Chip IEEE 802.11b/g/n 2T2R WLAN Controller 3
with PCI Express Interface
Track ID: JATR-1076-21 Rev. 1.1