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5P49V5901ADDDNLGI

PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5P49V5901

PROGRAMMABLE CLOCK GENERATOR

CLOCK SYNTHESIZER

Reference Clock Input Pins and

Selection

The IDT5P49V5901 supports up to two clock inputs. One of

the clock inputs (XIN/ REF) can be driven by either an

external crystal or a reference clock. The second clock input

(CLKIN, CLKINB) can only be driven from an external

reference clock. The CLKSEL pin selects the input clock

between either XTAL/REF or (CLKIN, CLKINB).

Either clock input can be set as the primary clock. The

primary clock designation is to establish which is the main

reference clock to the PLL. The non-primary clock is

designated as the secondary clock in case the primary clock

goes absent and a backup is needed. The PRIMSRC bit

determines which clock input will be selected as primary

clock. When PRIMSRC bit is “0”, XIN/REF is selected as the

primary clock, and when “1”, (CLKIN, CLKINB) as the

primary clock.

The two external reference clocks can be manually selected

using the CLKSEL pin. The SM bits must be set to “0x” for

manual switchover which is detailed in Manual Switchover

Mode section.

Crystal Input (XIN/REF)

The crystal used should be a fundamental mode quartz

crystal; overtone crystals should not be used.

When a crystal is connected across the XIN/REF and XOUT

pins it is important to set the internal tuning capacitor values

correctly to achieve the highest clock frequency accuracy.

There are two equal valued tuning capacitors, one for XIN

and one for XOUT and each capacitor provides a parallel

path for its associated pin to the internal ground of the

device. The values of these capacitors are composed of a

fixed capacity plus a variable capacity set with the XTAL[5:0]

register through the I2C interface. Adjustment of the crystal

tuning capacitors through firmware allows for maximum

flexibility to accommodate crystals from various

manufacturers. The range of tuning capacitor values

available are in accordance with the following table.

XTAL[5:0] Tuning Capacitor Characteristics

Parameter Bits Step (pF) Min (pF) Max (pF)

XTAL

6

0.5

0

16

The AC voltages on the XIN and XOUT pins are out of

phase, which allows the two XTAL[5:0] tuning capacitors to

be translated into a single equivalent parallel load capacitor

across XIN and XOUT by dividing the tuning capacity by

two. Adding the fixed parallel capacity and the effective

parallel tuning capacity set by XTAL results in the total

parallel tuning capacity provided by the VersaClock.

XTAL load cap = 4.5pF + (XTAL[5:0]/2) (Eq. 1)

Equation 1 and the table of XTAL[5:0] tuning capacitor

characteristics show that the parallel tuning capacitance

can be set between 4.5pF to 12.5pF with a resolution of 0.25

pF. Consider two examples.

For a crystal CL= 8pF, where CL is the parallel capacity

specified by the crystal vendor that sets the crystal

frequency to the nominal value. Under the assumptions that

the stray capacity between the crystal leads on the circuit

board is zero and that no external tuning caps are placed on

the crystal leads, then the internal parallel tuning capacity is

equal to the load capacity presented to the crystal by the

VersaClock. Equation 1 allows for the direct calculation that

XTAL[5:0] = 14 (dec).

In the case of a CL = 18pF crystal, the maximum internal

parallel tuning cap of 12.5pF will be insufficient. Two

external tuning capacitors must be added to the circuit

board, one on each of XIN and XOUT. For maximum turning

range, set the value of the two external tuning caps so that

XTAL[5:0] is set in the middle of its range, 8pF/2 = 4pF and

XTAL[5:0] = 32 (dec). Using Equation 1, the internal tuning

capacitor is set for 4.5pF + 4pF = 8.5pF. The remaining

tuning capacity is 18pF - 8.5pF = 9.5pF. Each external

tuning capacitor is then 2*9.5pF = 19pF.

The internal load capacitors are true parallel-plate

capacitors for ultra-linear performance. Parallel-plate

capacitors were chosen to reduce the frequency shift that

occurs when non-linear load capacitance interacts with

load, bias, supply, and temperature changes. External

non-linear crystal load capacitors should not be used for

applications that are sensitive to absolute frequency

requirements.

Manual Switchover Mode

When SM[1:0] is “0x”, the redundant inputs are in manual

switchover mode. In this mode, CLKSEL pin is used to

switch between the primary and secondary clock sources.

The primary and secondary clock source setting is

determined by the PRIMSRC bit. During the switchover, no

glitches will occur at the output of the device, although there

may be frequency and phase drift, depending on the exact

phase and frequency relationship between the primary and

secondary clocks.

IDT® PROGRAMMABLE CLOCK GENERATOR

5

IDT5P49V5901

REV A 031014

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