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IDT72V36100_06

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

Integrated Device Technology 

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

65,536 x 36 and 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS(1) — ASYNCHRONOUS TIMING

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

Commercial

Com’l & Ind’l

Symbol

fA(4)

tAA(4)

tCYC(4)

tCYH(4)

tCYL(4)

tRPE(4)

tFFA(4)

tEFA(4)

tPAFA(4)

tPAEA(4)

Parameter

Cycle Frequency (Asynchronous mode)

Data Access Time

Cycle Time

Cycle HIGH Time

Cycle LOW Time

Read Pulse after EF HIGH

Clock to Asynchronous FF

Clock to Asynchronous EF

Clock to Asynchronous Programmable Almost-Full Flag

Clock to Asynchronous Programmable Almost-Empty Flag

IDT72V36100L6

IDT72V36110L6

Min.

Max.

—

100

0.6

8

10

—

4.5

—

4.5

—

8

—

—

8

—

8

—

8

—

8

IDT72V36100L7-5

IDT72V36110L7-5

Min.

Max. Unit

—

83 MHz

0.6

10

ns

12

—

ns

5

—

ns

5

—

ns

10

—

ns

—

10

ns

—

10

ns

—

10

ns

—

10

ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Parameters apply to the PBGA package only.

10

APRIL 6, 2006

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