AN-8027 Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza

componentes Descripción

Lista de partido

AN-8027

FAN480X PFC+PWM Combination Controller Application

Fairchild Semiconductor 

AN-8027

ID

I D, AVG

ID, AVG = IBOUT (1− cos(4π ⋅ fLINE ⋅ t))

I BOUT

VBOUT ,RIPPLE

=

2π

I BOUT

f LINE CBOUT

VBOUT

Figure 14. PFC Output Voltage Ripple

(Design Example) With the ripple specification of

12VPP, the capacitor should be:

CBOUT

>

I BOUT

2π ⋅ fLINE ⋅VBOUT ,RIPPLE

=

0.9 = 239μ F

2π ⋅ 50 ⋅12

Since minimum allowable output voltage during one

cycle line (20ms) drop-outs is 310V, the capacitor

should be:

CBOUT

> PBOUT ⋅ tHOLD

VOUT 2 − VOUT ,MIN 2

=

2 ⋅ 349 ⋅ 20 ×10−3

3872 − 3102

= 260μF

Thus, 270μF capacitor is selected for the PFC output

capacitor.

Figure 15. Two-Level PFC Output Block

The voltage divider network for the PFC output voltage

sensing should be designed such that FBPFC voltage is

2.5V at nominal PFC output voltage:

VBOUT

×

RFB 2

RFB1 + RFB2

= 2.5V

(26)

(Design Example) Assuming the second level of

PFC output voltage is 347V:

RFB 2

=

(1 − VBOUT 2

VBOUT

)

⋅

20

2.5

×10−6

=

(1

−

347

387

)

⋅

20

2.5

× 10−6

= 12.9kΩ

13kΩ is selected for RFB2.

RFB1

= (VBOUT

2.5

−1) ⋅ RFB2

= (387 −1) ⋅13×103 = 1999kΩ

2.5

2MΩ is selected for RFB1.

[STEP-6] PFC Output Sensing Circuit

To improve system efficiency at low line and light load

condition, FAN480X provides two-level PFC output

voltage. As shown in Figure 15, FAN480X monitors VEA

and VRMS voltages to adjust the PFC output voltage.

The PFC output voltage when 20µA is enabled is given as:

VBOUT 2

= VBOUT

× (1-

20μA× RFB2 )

2.5

(25)

It is typical second boost output voltage as 340V~300V.

[STEP-7] PFC Current-Sensing Circuit Design

Figure 16 shows the PFC compensation circuits. The first

step in compensation network design is to select the current-

sensing resistor of PFC converter considering the control

window of voltage loop. Since line feed-forward is used in

FAN480X, the output power is proportional to the voltage

control error amplifier voltage as:

PBOUT

(VEA )

=

P MAX

BOUT

⋅ VEA − 0.6

V SAT

EA

− 0.6

(27)

where VEASAT is 5.6V and the maximum power limit of PFC

is:

P MAX

BOUT

=

V2

LINE . BO

⋅ GMAX

RIAC RCS1

⋅ RM

(28)

© 2009 Fairchild Semiconductor Corporation

Rev. 1.0.0 • 8/26/09

8

www.fairchildsemi.com

Share Link: