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ICS513M

LOCO™ PLL Clock Generator

Integrated Circuit Systems 

ICS513

LOCO™ PLL Clock Generator

Pin Assignment

X1/ICLK 1

VDD 2

GND 3

REF 4

8 X2

7 S1

6 S0

5 CLK

Clock Decoding Table (MHz) with

14.31818MHz Crystal or Clock Input

S1 S0

CLK

Multiplier Accuracy

0 0 Power Down CLK

-

-

01

100

6.984 1 ppm

M0

24

1.676 1 ppm

M1

14.31818

1

0 ppm

10

48

3.353 0.017%

11

3.6864

0.2576 0.044%

0 = connect directly to ground.

1 = connect directly to VDD.

M = leave unconnected (floating).

CLK and REF stop low in power down state.

Pin Descriptions

Number

1

2

3

4

5

6

7

8

Name

X1/ICLK

VDD

GND

REF

CLK

S0

S1

X2

Type

I

P

P

O

O

TI

TI

O

Description

Crystal connection to 14.31818 MHz crystal or clock input.

Connect to +3.3 V or +5 V.

Connect to ground.

Reference 14.31818 MHz crystal oscillator buffered clock output.

Clock output per table above.

Select 0 for output clock. Connect to GND or VDD or float. See table above.

Select 1 for output clock. Connect to GND or VDD or float. See table above.

Crystal connection to 14.31818 MHz crystal. Leave unconnected for clock input.

Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection

Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK output stops low.

The crystal oscillator and REF output are still active.

2. With a clock input, the phase relationship between the input and output clocks can change

each time the device is powered on.

If a fixed phase relationship is required, please use our ICS571 or other zero delay multiplier.

MDS 513 B

2

Revision 080699

Printed 12/4/00

Integrated Circuit Systems • 525 Race Street • San Jose • CA• 95126 • (408)295-9800tel• (408)295-9818fax

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