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IDT7016L

HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7016S/L

High-Speed 16K x 9 Dual-Port Static RAM

Waveform of Read Cycles(5)

ADDR

CE

tRC

tAA(4)

(4)

tACE

tAOE (4)

OE

Military, Industrial and Commercial Temperature Ranges

R/W

DATAOUT

tLZ (1)

tOH

VALID DATA(4)

BUSYOUT

tBDD(3,4)

tHZ(2)

3190 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, CE or OE.

3. tBDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation

to valid output data.

4. Start of valid data depends on which timing becomes effective last: tAOE,tACE,tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up / Power-Down

CE

tPU

ICC

50%

ISB

tPD

50%

,

3190 drw 08

6.842

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