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PDI1284P11 Datasheet PDF : 16 Pages
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Nexperia
PDI1284P11
3.3 V parallel interface transceiver/buffer
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
a. Input pulse definition
tW
90 %
VM
10 %
tr
tf
90 %
VM
10 %
tW
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VI
G
VCC
CL
VO
DUT
RT
RL
VEXT
GND
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b. Test circuit
CL = load capacitance includes jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance of the pulse generator.
Test conditions for propagation delays are given in Table 10, test conditions for slew rate are given in Table 8
Fig 8. Test circuit for An, Bn and Yn outputs; slew rate B/Y side
Table 10. Test conditions for An, Bn and Yn outputs
Output
VI
VM
Repetition tW
rate
tr
tf
An
Bn, Yn
3.0 V
3.0 V
1.5 V
1.5 V
1 MHz
1 MHz
500 ns
3 ns
3 ns
500 ns
3 ns
3 ns
Switch position
tPLH, tPZH
GND
tPHL, tPHZ
GND
GND
VEXT = 2.8 V
VCC
DUT
IO
VCC / 2
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IO is measured by forcing 0.5VCC on the output. The output impedance can then be calculated as Ro = 0.5VCC / |IO|.
Fig 9. Output impedance
PDI1284P11_3
Product data sheet
Rev. 03 — 25 August 2008
© Nexperia B.V. 2017. All rights reserved
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