TDA7330 Ver la hoja de datos (PDF) - STMicroelectronics
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TDA7330 Datasheet PDF : 9 Pages
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TDA7330B
ELECTRICAL CHARACTERISTICS (VCC = 5V, Tamb = 25°C; Rg = 600Ω; fosc = 4.332MHz;
VIN = 20mVrms unless otherwise specified)
Symbol
SUPPLY
Parameter
Test Condition
Min. Typ. Max. Unit
VCC
IS
RPOR
Supply Voltage
Supply Current
POR Pull Down Resistor
PORON POR Threshold
FILTER(measured an pin 4 FILOUT)
pin 20
4.5
5
5.5
V
9
mA
40
KΩ
2.5
V
FC
Center Frequency
BW
3dB Bandwidth
56.5 57 57.5 KHz
2.5
3
3.5 KHz
G
Gain
f = 57KHz
18
20
22
dB
A
Attenuation
∆Ph Phase non linearity
∆f = +4KHz
f = 38KHz; Vi = 500mVrms
f = 67KHz; Vi = 250mVrms
A (see note1)
B (see note1)
C (see note1)
18
22
dB
50
80
dB
35
50
dB
0.5
5
DEG
1
7.5 DEG
2
10 DEG
Ri
Input Impedance
100 160 200 KΩ
S/N Signal to Noise Ratio
Vi = 3mVrms
30
40
dB
Vi
Maximum Input Signal Capability f = 19KHz; T3 < –40dB (see note2)
f = 57KHz (RDS + ARI)
1
Vrms
50 mVrms
RL
Load Impedance
Pin 4
100
KΩ
CROSS DETECTOR
RA
Resistance pin 3-4
OSCILLATOR
15
21
28
KΩ
FOSC
VCLL
VCLH
Oscillator Frequency
Clock Input level LOW (pin 10)
Clock Input Level HIGH (pin 10)
Output Amplitude (pin 9)
FSEL = Open (*)
FSEL = Closed to VCC (**)
4.332
8.664
1
4
4.5
MHz
MHz
V
V
VPP
(*) FSEL pin has an internal 40KΩ pull down resistor A 4.332MHz QUARTZ must be used (**) A 8.664MHz QUARTZ must be used.
DEMODULATOR
∆fO
SRDS
SARI
Tlock
VOH
VOL
fRDS
tD
Max Oscillator Deviation
RDS Detection Sensitivity
ARI Detection Sensitivity
RDS Lockup Time
Output HIGH Voltage
Output LOW Voltage
Data Rate for RDS
RDDA Transition versus RDCL
FSEL = Open
IL = 0.5mA; pins 12, 13, 14, 15
IL = 0.5mA; pins 12, 13, 14, 15
RDCL pin
(see figure 2)
Note(1):
The phase non linearity is defined as: ∆Ph = | -2 φf2 + φf1 + φf3 |
where φfx is the input-output phase difference at the frequency fx (x = 1,2,3)
+ 1.2
KHz
1
mVrms
3
mVrms
100
ms
4
V
1
V
1187.5
Hz
4.3
µsec
3/9
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