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MC74VHC244

Octal Bus Buffer

ON Semiconductor 

MC74VHC244

Octal Bus Buffer

The MC74VHC244 is an advanced high speed CMOS octal bus

buffer fabricated with silicon gate CMOS technology.

The MC74VHC244 is a noninverting 3–state buffer, and has two

active–low output enables. This device is designed to be used with

3–state memory address drivers, etc.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems

to 3 V systems.

• High Speed: tPD = 3.9 ns (Typ) at VCC = 5 V

• Low Power Dissipation: ICC = 4 µA (Max) at TA = 25°C

• High Noise Immunity: VNIH = VNIL = 28% VCC

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2 V to 5.5 V Operating Range

• Low Noise: VOLP = 0.9 V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300 mA

• ESD Performance: HBM > 2000 V; Machine Model > 200 V

• Chip Complexity: 136 FETs

This device contains protection circuitry to guard against damage due to

high static voltages or electric fields. However, precautions must be taken to

avoid applications of any voltage higher than maximum rated voltages to

this high–impedance circuit. For proper operation, Vin and Vout should be

constrained to the range GND v (Vin or Vout) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either GND or VCC). Unused outputs must be left open.

A1 2

18 YA1

A2 4

A3 6

DATA

INPUTS

A4 8

B1 11

B2 13

16 YA2

14 YA3

12 YA4

NONINVERTING

9 YB1 OUTPUTS

7 YB2

B3 15

5 YB3

B4 17

3 YB4

OUTPUT

ENABLES

OEA 1

OEB 19

Figure 1. LOGIC DIAGRAM

http://onsemi.com

DEVICE MARKING

20

VHC244

AWLYYWW

1

DW SUFFIX

20–LEAD SOIC WIDE PACKAGE

CASE 751D

VHC

20

1

244

ALYW

DT SUFFIX

20–LEAD TSSOP PACKAGE

CASE 948E

20

1

M SUFFIX

74VHC244

AWLYWW

20–LEAD SOIC EIAJ PACKAGE

CASE 967

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

PIN ASSIGNMENT

OEA 1

A1 2

YB4 3

A2 4

YB3 5

A3 6

YB2 7

A4 8

YB1 9

GND 10

20 VCC

19 OEB

18 YA1

17 B4

16 YA2

15 B3

14 YA3

13 B2

12 YA4

11 B1

ORDERING INFORMATION

See detailed ordering and shipping information in the

Ordering Information Table on page 3 of this data sheet.

© Semiconductor Components Industries, LLC, 2001

1

December, 2001 – Rev. 5

Publication Order Number:

MC74VHC244/D

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